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[PATHC OLK-6.6 v3 0/8] memcg reclaim and cgroup kill
by Lu Jialin 11 Dec '23

11 Dec '23

Lu Jialin (8): cgroup: Export cgroup.kill from cgroupv2 to cgroupv1 memcg: Export memcg.{min/low} from cgroupv2 to cgroupv1 memcg: Export memcg.high from cgroupv2 to cgroupv1 memcg: Export memory.events{local} from cgroupv2 to cgroupv1 memcg: enable memcg async reclaim memcg: export high_async_ratio to userland memcg: introduce per-memcg reclaim interface config: enable CONFIG_MEMCG_V1_RECLAIM and CONFIG_CGROUP_V1_KILL arch/arm64/configs/openeuler_defconfig | 2 + arch/x86/configs/openeuler_defconfig | 2 + include/linux/memcontrol.h | 24 +++- init/Kconfig | 10 ++ kernel/cgroup/cgroup-internal.h | 3 + kernel/cgroup/cgroup-v1.c | 7 + kernel/cgroup/cgroup.c | 4 +- mm/memcontrol.c | 184 ++++++++++++++++++++++++- 8 files changed, 229 insertions(+), 7 deletions(-) -- 2.34.1

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[PATCH v6 OLK-6.6 0/5] Support Qos Scheduler
by Wenyu Huang 11 Dec '23

11 Dec '23

Zhang Qiao (5): sched: Introduce qos scheduler for co-location sched: Throttle qos cfs_rq when current cpu is running online task sched: Support kill boost for offline task sched: Introduce handle priority reversion mechanism sched: Enable qos scheduler config arch/arm64/configs/openeuler_defconfig | 1 + arch/x86/configs/openeuler_defconfig | 1 + include/linux/cgroup.h | 4 + include/linux/resume_user_mode.h | 5 + include/linux/sched.h | 11 + init/Kconfig | 12 + kernel/cgroup/cgroup.c | 22 ++ kernel/sched/core.c | 155 ++++++++++ kernel/sched/fair.c | 378 ++++++++++++++++++++++++- kernel/sched/sched.h | 12 + kernel/signal.c | 3 + 11 files changed, 603 insertions(+), 1 deletion(-) -- 2.34.1

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[PATCH v2 OLK-5.10] iommu/arm-smmu-v3: Add a SYNC command to avoid broken page table prefetch
by Zhang Zekun 11 Dec '23

11 Dec '23

hulk inclusion category: bugfix bugzilla: https://gitee.com/src-openeuler/kernel/issues/I8MVBZ CVE: NA ----------------------------------------------- On Hisilicon LINXICORE9100 cores, SMMU pagetable prefetch features may prefetch and use a invalid PTE even the PTE is valid at that time. This will cause the device trigger fake pagefaults. If the SMMU works in terminate mode, transactions which occur fake pagefaults will be aborted, and could result in unexpected errors. To fix this problem, we need to add a SYNC command after smmu has map a iova, then smmu will always try to get the newest PTE. Signed-off-by: Zhang Zekun <zhangzekun11(a)huawei.com> --- v2: - add a config to explictly set erratum config, no code logic change Documentation/arm64/silicon-errata.rst | 2 ++ arch/arm64/Kconfig | 13 +++++++++++++ arch/arm64/configs/openeuler_defconfig | 1 + arch/arm64/include/asm/cpucaps.h | 1 + arch/arm64/kernel/cpu_errata.c | 14 ++++++++++++++ drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 20 ++++++++++++++++++++ 6 files changed, 51 insertions(+) diff --git a/Documentation/arm64/silicon-errata.rst b/Documentation/arm64/silicon-errata.rst index a9441bfebb0d..1f06e18a1859 100644 --- a/Documentation/arm64/silicon-errata.rst +++ b/Documentation/arm64/silicon-errata.rst @@ -156,6 +156,8 @@ stable kernels. +----------------+-----------------+-----------------+-----------------------------+ | Hisilicon | LINXICORE9100 | #162100125 | HISILICON_ERRATUM_162100125 | +----------------+-----------------+-----------------+-----------------------------+ +| Hisilicon | LINXICORE9100 | #162100602 | HISILICON_ERRATUM_162100602 | ++----------------+-----------------+-----------------+-----------------------------+ | Hisilicon | HIP09 | #162102203 | HISILICON_ERRATUM_162102203 | +----------------+-----------------+-----------------+-----------------------------+ | Qualcomm Tech. | Kryo/Falkor v1 | E1003 | QCOM_FALKOR_ERRATUM_1003 | diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig index c5eca65c27fc..851d24a35e4e 100644 --- a/arch/arm64/Kconfig +++ b/arch/arm64/Kconfig @@ -836,6 +836,19 @@ config HISILICON_ERRATUM_162102203 If unsure, say N. +config HISILICON_ERRATUM_162100602 + bool "Hisilicon erratum 162100602" + depends on ARM_SMMU_V3 + default y + help + On Hisilicon LINXICORE9100 cores, SMMU pagetable prefetch features may + prefetch and use a invalid PTE even the PTE is valid at that time. This + will cause the device trigger fake pagefaults. If the SMMU works in + terminate mode, transactions which occur fake pagefaults will be aborted, + and could result in unexpected errors. + + If unsure, say Y. + config QCOM_FALKOR_ERRATUM_1003 bool "Falkor E1003: Incorrect translation due to ASID change" default y diff --git a/arch/arm64/configs/openeuler_defconfig b/arch/arm64/configs/openeuler_defconfig index edcb7911b3ce..261023a908a8 100644 --- a/arch/arm64/configs/openeuler_defconfig +++ b/arch/arm64/configs/openeuler_defconfig @@ -404,6 +404,7 @@ CONFIG_HISILICON_ERRATUM_1980005=y CONFIG_HISILICON_ERRATUM_162100801=y CONFIG_HISILICON_ERRATUM_162100125=y CONFIG_HISILICON_ERRATUM_162102203=y +CONFIG_HISILICON_ERRATUM_162100602=y CONFIG_QCOM_FALKOR_ERRATUM_1003=y CONFIG_QCOM_FALKOR_ERRATUM_1009=y CONFIG_QCOM_QDF2400_ERRATUM_0065=y diff --git a/arch/arm64/include/asm/cpucaps.h b/arch/arm64/include/asm/cpucaps.h index ce9fbf260a3c..0220f10cddd7 100644 --- a/arch/arm64/include/asm/cpucaps.h +++ b/arch/arm64/include/asm/cpucaps.h @@ -81,6 +81,7 @@ #define ARM64_HAS_PBHA_STAGE2 73 #define ARM64_SME 74 #define ARM64_SME_FA64 75 +#define ARM64_WORKAROUND_HISILICON_ERRATUM_162100602 76 #define ARM64_NCAPS 80 diff --git a/arch/arm64/kernel/cpu_errata.c b/arch/arm64/kernel/cpu_errata.c index 7f175b3aac15..6a3e948d5c2c 100644 --- a/arch/arm64/kernel/cpu_errata.c +++ b/arch/arm64/kernel/cpu_errata.c @@ -331,6 +331,13 @@ static const struct midr_range hisilicon_erratum_162100125_cpus[] = { }; #endif +#ifdef CONFIG_HISILICON_ERRATUM_162100602 +static const struct midr_range hisilicon_erratum_162100602_cpus[] = { + MIDR_REV(MIDR_HISI_LINXICORE9100, 0, 0), + {}, +}; +#endif + #ifdef CONFIG_QCOM_FALKOR_ERRATUM_1003 static const struct arm64_cpu_capabilities qcom_erratum_1003_list[] = { { @@ -533,6 +540,13 @@ const struct arm64_cpu_capabilities arm64_errata[] = { ERRATA_MIDR_RANGE_LIST(hisilicon_erratum_162100125_cpus), }, #endif +#ifdef CONFIG_HISILICON_ERRATUM_162100602 + { + .desc = "Hisilicon erratum 162100602", + .capability = ARM64_WORKAROUND_HISILICON_ERRATUM_162100602, + ERRATA_MIDR_RANGE_LIST(hisilicon_erratum_162100602_cpus), + }, +#endif #ifdef CONFIG_QCOM_FALKOR_ERRATUM_1003 { .desc = "Qualcomm Technologies Falkor/Kryo erratum 1003", diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c index a55c2dab72f8..458151b7fab2 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -2941,6 +2941,23 @@ static void arm_smmu_iotlb_sync(struct iommu_domain *domain, gather->pgsize, true, smmu_domain); } +#ifdef CONFIG_HISILICON_ERRATUM_162100602 +static void arm_smmu_iotlb_sync_map(struct iommu_domain *domain, + unsigned long iova, size_t size) +{ + struct arm_smmu_domain *smmu_domain = to_smmu_domain(domain); + size_t granule_size; + + if (!cpus_have_const_cap(ARM64_WORKAROUND_HISILICON_ERRATUM_162100602)) + return; + + granule_size = 1 << __ffs(smmu_domain->domain.pgsize_bitmap); + + /* Add a SYNC command to sync io-pgtale to avoid errors in pgtable prefetch*/ + arm_smmu_tlb_inv_range_domain(iova, granule_size, granule_size, true, smmu_domain); +} +#endif + static phys_addr_t arm_smmu_iova_to_phys(struct iommu_domain *domain, dma_addr_t iova) { @@ -3970,6 +3987,9 @@ static struct iommu_ops arm_smmu_ops = { .unmap = arm_smmu_unmap, .flush_iotlb_all = arm_smmu_flush_iotlb_all, .iotlb_sync = arm_smmu_iotlb_sync, +#ifdef CONFIG_HISILICON_ERRATUM_162100602 + .iotlb_sync_map = arm_smmu_iotlb_sync_map, +#endif .iova_to_phys = arm_smmu_iova_to_phys, .probe_device = arm_smmu_probe_device, .release_device = arm_smmu_release_device, -- 2.17.1

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[PATCH OLK-6.6 0/2] cgroup v1 writeback enable
by chenridong 11 Dec '23

11 Dec '23

Lu Jialin (2): cgroup: support cgroup writeback on cgroupv1 openeuler_defconfig: enable CONFIG_CGROUP_V1_WRITEBACK in openeuler_defconfig for x86 and arm64 arch/arm64/configs/openeuler_defconfig | 1 + arch/x86/configs/openeuler_defconfig | 1 + block/blk-cgroup.c | 3 + block/blk-cgroup.h | 3 + include/linux/backing-dev.h | 29 +++++- include/linux/cgroup-defs.h | 2 + include/linux/cgroup.h | 1 + include/linux/memcontrol.h | 5 ++ init/Kconfig | 5 ++ kernel/cgroup/cgroup.c | 28 ++++-- mm/backing-dev.c | 117 ++++++++++++++++++++++++- mm/memcontrol.c | 83 +++++++++++++++++- 12 files changed, 264 insertions(+), 14 deletions(-) -- 2.34.1

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[PATCH OLK-6.6 v3] config: Open CONFIG_AARCH32_EL0 and keep CONFIG_ARM64_ILP32 closed
by Jinjie Ruan 11 Dec '23

11 Dec '23

hulk inclusion category: bugfix bugzilla: https://gitee.com/openeuler/kernel/issues/I8JVJ3 CVE: NA ------------------------------------------------------------------------- No one currently uses IPL32, keep it closed to simplify the code logic of TASK_SIZE_MAX, thereby improving benchmark performance. For example, all test items of libMicro can be improved by 4.89% on average. Since commit dbece8b041f3 ("arm64: rename COMPAT to AARCH32_EL0"), CONFIG_COMPAT has been renamed to CONFIG_AARCH32_EL0, so open CONFIG_AARCH32_EL0 as what CONFIG_COMPAT used to be. And as commit 880fd21c0a46 ("arm64: set 32-bit compatible TASK_SIZE_MAX to fix U32 libc_write_01 error") said, not set CONFIG_COMPAT_TASK_SIZE by default. Signed-off-by: Zhen Lei <thunder.leizhen(a)huawei.com> Reviewed-by: Cheng Jian <cj.chengjian(a)huawei.com> Reviewed-by: Liu Chao (CR) <liuchao173(a)huawei.com> Reviewed-by: Xiongfeng Wang <wangxiongfeng2(a)huawei.com> Signed-off-by: Zheng Zengkai <zhengzengkai(a)huawei.com> Signed-off-by: Jinjie Ruan <ruanjinjie(a)huawei.com> --- v3: - Update the commit subject and message to make it clear. v2: - Do not touch the makeconfig.sh. --- arch/arm64/configs/openeuler_defconfig | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/arch/arm64/configs/openeuler_defconfig b/arch/arm64/configs/openeuler_defconfig index 9d2f717c1f7c..ce5a7aeaeeca 100644 --- a/arch/arm64/configs/openeuler_defconfig +++ b/arch/arm64/configs/openeuler_defconfig @@ -449,9 +449,10 @@ CONFIG_MITIGATE_SPECTRE_BRANCH_HISTORY=y # CONFIG_RODATA_FULL_DEFAULT_ENABLED is not set # CONFIG_ARM64_SW_TTBR0_PAN is not set CONFIG_ARM64_TAGGED_ADDR_ABI=y -CONFIG_COMPAT=y +CONFIG_AARCH32_EL0=y # CONFIG_KUSER_HELPERS is not set # CONFIG_COMPAT_ALIGNMENT_FIXUPS is not set +# CONFIG_COMPAT_TASK_SIZE is not set CONFIG_ARMV8_DEPRECATED=y CONFIG_SWP_EMULATION=y CONFIG_CP15_BARRIER_EMULATION=y @@ -526,6 +527,8 @@ CONFIG_EFI=y CONFIG_DMI=y # end of Boot options +CONFIG_COMPAT=y + # # Power management options # -- 2.34.1

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[PATCH OLK-6.6 0/2] cgroup v1 writeback enable
by chenridong 11 Dec '23

11 Dec '23

Lu Jialin (2): cgroup: support cgroup writeback on cgroupv1 openeuler_defconfig: enable CONFIG_CGROUP_V1_WRITEBACK in openeuler_defconfig for x86 and arm64 arch/arm64/configs/openeuler_defconfig | 1 + arch/x86/configs/openeuler_defconfig | 1 + block/blk-cgroup.c | 3 + block/blk-cgroup.h | 3 + include/linux/backing-dev.h | 29 +++++- include/linux/cgroup-defs.h | 2 + include/linux/cgroup.h | 1 + include/linux/memcontrol.h | 5 ++ init/Kconfig | 5 ++ kernel/cgroup/cgroup.c | 28 ++++-- mm/backing-dev.c | 117 ++++++++++++++++++++++++- mm/memcontrol.c | 83 +++++++++++++++++- 12 files changed, 264 insertions(+), 14 deletions(-) -- 2.34.1

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[PATCH OLK-6.6 0/2] cgroup v1 writeback enable
by chenridong 11 Dec '23

11 Dec '23

Lu Jialin (2): cgroup: support cgroup writeback on cgroupv1 openeuler_defconfig: enable CONFIG_CGROUP_V1_WRITEBACK in openeuler_defconfig for x86 and arm64 arch/arm64/configs/openeuler_defconfig | 1 + arch/x86/configs/openeuler_defconfig | 1 + block/blk-cgroup.c | 3 + block/blk-cgroup.h | 3 + include/linux/backing-dev.h | 29 +++++- include/linux/cgroup-defs.h | 2 + include/linux/cgroup.h | 1 + include/linux/memcontrol.h | 5 ++ init/Kconfig | 5 ++ kernel/cgroup/cgroup.c | 28 ++++-- mm/backing-dev.c | 117 ++++++++++++++++++++++++- mm/memcontrol.c | 83 +++++++++++++++++- 12 files changed, 264 insertions(+), 14 deletions(-) -- 2.34.1

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[PATCH OLK-6.6 0/5] LoongArch: add cpufreq and ls2k500 bmc support
by Hongchen Zhang 11 Dec '23

11 Dec '23

Chong Qiao (4): fbdev: add ls2k500sfb driver for ls2k500 bmc. ipmi: add ls2k500 bmc ipmi support. LoongArch: defconfig: enable CONFIG_FB_LS2K500=m. LoongArch: fix ls2k500 bmc not work when installing iso liuyun (1): cpufreq: Add cpufreq driver for LoongArch arch/loongarch/Kconfig | 1 + arch/loongarch/configs/loongson3_defconfig | 5 + arch/loongarch/include/asm/fpu.h | 13 +- drivers/char/ipmi/Makefile | 4 + drivers/char/ipmi/btlock.h | 92 ++ drivers/char/ipmi/ipmi_si.h | 11 + drivers/char/ipmi/ipmi_si_intf.c | 4 + drivers/char/ipmi/ipmi_si_ls2k500.c | 173 +++ drivers/char/ipmi/kcs_bmc_ls2k500.h | 67 + drivers/cpufreq/Kconfig | 11 + drivers/cpufreq/Makefile | 1 + drivers/cpufreq/loongson3-acpi-cpufreq.c | 1527 ++++++++++++++++++++ drivers/gpu/drm/loongson/loongson_module.c | 15 + drivers/video/fbdev/Kconfig | 13 + drivers/video/fbdev/Makefile | 1 + drivers/video/fbdev/ls2k500sfb.c | 792 ++++++++++ 16 files changed, 2729 insertions(+), 1 deletion(-) create mode 100644 drivers/char/ipmi/btlock.h create mode 100644 drivers/char/ipmi/ipmi_si_ls2k500.c create mode 100644 drivers/char/ipmi/kcs_bmc_ls2k500.h create mode 100644 drivers/cpufreq/loongson3-acpi-cpufreq.c create mode 100644 drivers/video/fbdev/ls2k500sfb.c -- 2.33.0

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[PATCH 0/5] LoongArch: add cpufreq and ls2k500 bmc support
by Hongchen Zhang 11 Dec '23

11 Dec '23

Chong Qiao (4): fbdev: add ls2k500sfb driver for ls2k500 bmc. ipmi: add ls2k500 bmc ipmi support. LoongArch: defconfig: enable CONFIG_FB_LS2K500=m. LoongArch: fix ls2k500 bmc not work when installing iso liuyun (1): cpufreq: Add cpufreq driver for LoongArch arch/loongarch/Kconfig | 1 + arch/loongarch/configs/loongson3_defconfig | 5 + arch/loongarch/include/asm/fpu.h | 13 +- drivers/char/ipmi/Makefile | 4 + drivers/char/ipmi/btlock.h | 92 ++ drivers/char/ipmi/ipmi_si.h | 11 + drivers/char/ipmi/ipmi_si_intf.c | 4 + drivers/char/ipmi/ipmi_si_ls2k500.c | 173 +++ drivers/char/ipmi/kcs_bmc_ls2k500.h | 67 + drivers/cpufreq/Kconfig | 11 + drivers/cpufreq/Makefile | 1 + drivers/cpufreq/loongson3-acpi-cpufreq.c | 1527 ++++++++++++++++++++ drivers/gpu/drm/loongson/loongson_module.c | 15 + drivers/video/fbdev/Kconfig | 13 + drivers/video/fbdev/Makefile | 1 + drivers/video/fbdev/ls2k500sfb.c | 792 ++++++++++ 16 files changed, 2729 insertions(+), 1 deletion(-) create mode 100644 drivers/char/ipmi/btlock.h create mode 100644 drivers/char/ipmi/ipmi_si_ls2k500.c create mode 100644 drivers/char/ipmi/kcs_bmc_ls2k500.h create mode 100644 drivers/cpufreq/loongson3-acpi-cpufreq.c create mode 100644 drivers/video/fbdev/ls2k500sfb.c -- 2.33.0

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[PATCH OLK-5.10] smart_grid: cpufreq: clear offline and isolated CPU in warm CPUs
by Yipeng Zou 11 Dec '23

11 Dec '23

hulk inclusion category: bugfix bugzilla: https://gitee.com/openeuler/kernel/issues/I8MFO6 CVE: NA ---------------------------------------- When there has some CPU has been offline or isolated, the warm zone CPUs will not clear these CPUs. Because of the warm zone were saluted by a complement of hot zone. So, we need to clear offline and isolated CPUs in every time's warm zone CPUs update. Fixes: 6a00891859d8 ("smart_grid: cpufreq: introduce smart_grid cpufreq control") Signed-off-by: Yipeng Zou <zouyipeng(a)huawei.com> --- kernel/sched/grid/qos.c | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/kernel/sched/grid/qos.c b/kernel/sched/grid/qos.c index f8c5deffd3ea..7ee3687347ce 100644 --- a/kernel/sched/grid/qos.c +++ b/kernel/sched/grid/qos.c @@ -179,6 +179,7 @@ int sched_grid_zone_update(bool is_locked) raw_spin_lock_irqsave(&sg_zone.lock, flags); cpumask_clear(&sg_zone.cpus[SMART_GRID_ZONE_HOT]); + cpumask_clear(&sg_zone.cpus[SMART_GRID_ZONE_WARM]); list_for_each(pos, &sg_zone.af_list_head) { af_pos = list_entry(pos, struct auto_affinity, af_list); @@ -190,10 +191,14 @@ int sched_grid_zone_update(bool is_locked) cpumask_or(&sg_zone.cpus[SMART_GRID_ZONE_HOT], &sg_zone.cpus[SMART_GRID_ZONE_HOT], af_pos->ad.domains[af_pos->ad.curr_level]); + /* Update warm zone CPUs to max level first */ + cpumask_or(&sg_zone.cpus[SMART_GRID_ZONE_WARM], &sg_zone.cpus[SMART_GRID_ZONE_WARM], + af_pos->ad.domains[af_pos->ad.dcount - 1]); } - cpumask_complement(&sg_zone.cpus[SMART_GRID_ZONE_WARM], - &sg_zone.cpus[SMART_GRID_ZONE_HOT]); + /* Then reset warm zone CPUs without hot zone CPUs */ + cpumask_andnot(&sg_zone.cpus[SMART_GRID_ZONE_WARM], &sg_zone.cpus[SMART_GRID_ZONE_WARM], + &sg_zone.cpus[SMART_GRID_ZONE_HOT]); if (!is_locked) raw_spin_unlock_irqrestore(&sg_zone.lock, flags); -- 2.34.1

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