[PATCH openEuler-1.0-LTS 3/3] drivers : remove drivers/mtd/hisilicon/sfc

From: fengsheng fengsheng5@huawei.com

driver inclusion category: feature bugzilla: https://gitee.com/openeuler/kernel/issues/I4IYX7?from=project-issue CVE: NA

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This driver is not in use. Remove it.

Signed-off-by: fengsheng fengsheng5@huawei.com Reviewed-by: lidongming lidongming5@huawei.com Reviewed-by: ouyang delong ouyangdelong@huawei.com Acked-by: Xie XiuQi xiexiuqi@huawei.com Signed-off-by: Yang Yingliang yangyingliang@huawei.com --- MAINTAINERS | 5 - arch/arm64/configs/hulk_defconfig | 1 - arch/arm64/configs/openeuler_defconfig | 2 - arch/arm64/configs/storage_ci_defconfig | 1 - arch/arm64/configs/syzkaller_defconfig | 1 - arch/x86/configs/openeuler_defconfig | 1 - arch/x86/configs/storage_ci_defconfig | 1 - drivers/mtd/Kconfig | 2 - drivers/mtd/Makefile | 2 +- drivers/mtd/hisilicon/Kconfig | 1 - drivers/mtd/hisilicon/Makefile | 1 - drivers/mtd/hisilicon/sfc/Kconfig | 3 - drivers/mtd/hisilicon/sfc/Makefile | 3 - drivers/mtd/hisilicon/sfc/hrd_common.h | 106 -- drivers/mtd/hisilicon/sfc/hrd_sfc_driver.c | 242 ---- drivers/mtd/hisilicon/sfc/hrd_sflash_core.c | 539 -------- drivers/mtd/hisilicon/sfc/hrd_sflash_core.h | 160 --- drivers/mtd/hisilicon/sfc/hrd_sflash_driver.c | 390 ------ drivers/mtd/hisilicon/sfc/hrd_sflash_driver.h | 105 -- drivers/mtd/hisilicon/sfc/hrd_sflash_hal.c | 1159 ----------------- drivers/mtd/hisilicon/sfc/hrd_sflash_hal.h | 31 - drivers/mtd/hisilicon/sfc/hrd_sflash_spec.h | 376 ------ 22 files changed, 1 insertion(+), 3131 deletions(-) delete mode 100644 drivers/mtd/hisilicon/Kconfig delete mode 100644 drivers/mtd/hisilicon/Makefile delete mode 100644 drivers/mtd/hisilicon/sfc/Kconfig delete mode 100644 drivers/mtd/hisilicon/sfc/Makefile delete mode 100644 drivers/mtd/hisilicon/sfc/hrd_common.h delete mode 100644 drivers/mtd/hisilicon/sfc/hrd_sfc_driver.c delete mode 100644 drivers/mtd/hisilicon/sfc/hrd_sflash_core.c delete mode 100644 drivers/mtd/hisilicon/sfc/hrd_sflash_core.h delete mode 100644 drivers/mtd/hisilicon/sfc/hrd_sflash_driver.c delete mode 100644 drivers/mtd/hisilicon/sfc/hrd_sflash_driver.h delete mode 100644 drivers/mtd/hisilicon/sfc/hrd_sflash_hal.c delete mode 100644 drivers/mtd/hisilicon/sfc/hrd_sflash_hal.h delete mode 100644 drivers/mtd/hisilicon/sfc/hrd_sflash_spec.h

diff --git a/MAINTAINERS b/MAINTAINERS index de1f5d368ca88..d95d71e0ba4eb 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -5904,11 +5904,6 @@ F: drivers/ptp/ptp_qoriq.c F: include/linux/fsl/ptp_qoriq.h F: Documentation/devicetree/bindings/ptp/ptp-qoriq.txt

-HISILICON SFC DRIVER -M: Feng Sheng fengsheng5@huawei.com -S: Maintained -F: drivers/mtd/hisilicon/sfc/ - FREESCALE QUAD SPI DRIVER M: Han Xu han.xu@nxp.com L: linux-mtd@lists.infradead.org diff --git a/arch/arm64/configs/hulk_defconfig b/arch/arm64/configs/hulk_defconfig index 97354a29c914c..413667c434ee6 100644 --- a/arch/arm64/configs/hulk_defconfig +++ b/arch/arm64/configs/hulk_defconfig @@ -1818,7 +1818,6 @@ CONFIG_MTD=m # CONFIG_MTD_CMDLINE_PARTS is not set # CONFIG_MTD_AFS_PARTS is not set CONFIG_MTD_OF_PARTS=m -CONFIG_MTD_HISILICON_SFC=m # CONFIG_MTD_AR7_PARTS is not set

# diff --git a/arch/arm64/configs/openeuler_defconfig b/arch/arm64/configs/openeuler_defconfig index 06d57fc62c324..c63a2f829db02 100644 --- a/arch/arm64/configs/openeuler_defconfig +++ b/arch/arm64/configs/openeuler_defconfig @@ -1905,14 +1905,12 @@ CONFIG_MTD_SPI_NOR=m CONFIG_MTD_MT81xx_NOR=m CONFIG_MTD_SPI_NOR_USE_4K_SECTORS=y # CONFIG_SPI_CADENCE_QUADSPI is not set -CONFIG_SPI_HISI_SFC=m CONFIG_MTD_UBI=m CONFIG_MTD_UBI_WL_THRESHOLD=4096 CONFIG_MTD_UBI_BEB_LIMIT=20 # CONFIG_MTD_UBI_FASTMAP is not set CONFIG_MTD_UBI_GLUEBI=m # CONFIG_MTD_UBI_BLOCK is not set -CONFIG_MTD_HISILICON_SFC=m CONFIG_DTC=y CONFIG_OF=y # CONFIG_OF_UNITTEST is not set diff --git a/arch/arm64/configs/storage_ci_defconfig b/arch/arm64/configs/storage_ci_defconfig index 6d671761fd080..941f76b15c099 100644 --- a/arch/arm64/configs/storage_ci_defconfig +++ b/arch/arm64/configs/storage_ci_defconfig @@ -1061,7 +1061,6 @@ CONFIG_MTD_UBI_BEB_LIMIT=20 CONFIG_MTD_UBI_FASTMAP=y CONFIG_MTD_UBI_GLUEBI=y CONFIG_MTD_UBI_BLOCK=y -CONFIG_MTD_HISILICON_SFC=m CONFIG_DTC=y CONFIG_OF=y # CONFIG_OF_UNITTEST is not set diff --git a/arch/arm64/configs/syzkaller_defconfig b/arch/arm64/configs/syzkaller_defconfig index caa022e24fdc3..d82959f4027cf 100644 --- a/arch/arm64/configs/syzkaller_defconfig +++ b/arch/arm64/configs/syzkaller_defconfig @@ -1772,7 +1772,6 @@ CONFIG_MTD=m # CONFIG_MTD_CMDLINE_PARTS is not set # CONFIG_MTD_AFS_PARTS is not set CONFIG_MTD_OF_PARTS=m -CONFIG_MTD_HISILICON_SFC=m # CONFIG_MTD_AR7_PARTS is not set

# diff --git a/arch/x86/configs/openeuler_defconfig b/arch/x86/configs/openeuler_defconfig index 035d4b454dc80..854f10c491880 100644 --- a/arch/x86/configs/openeuler_defconfig +++ b/arch/x86/configs/openeuler_defconfig @@ -1943,7 +1943,6 @@ CONFIG_MTD_UBI_BEB_LIMIT=20 # CONFIG_MTD_UBI_FASTMAP is not set # CONFIG_MTD_UBI_GLUEBI is not set # CONFIG_MTD_UBI_BLOCK is not set -CONFIG_MTD_HISILICON_SFC=m # CONFIG_OF is not set CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y CONFIG_PARPORT=m diff --git a/arch/x86/configs/storage_ci_defconfig b/arch/x86/configs/storage_ci_defconfig index d18d5fcb90b37..51df58940ac6e 100644 --- a/arch/x86/configs/storage_ci_defconfig +++ b/arch/x86/configs/storage_ci_defconfig @@ -1200,7 +1200,6 @@ CONFIG_MTD_UBI_BEB_LIMIT=20 CONFIG_MTD_UBI_FASTMAP=y CONFIG_MTD_UBI_GLUEBI=y CONFIG_MTD_UBI_BLOCK=y -CONFIG_MTD_HISILICON_SFC=m # CONFIG_OF is not set CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y # CONFIG_PARPORT is not set diff --git a/drivers/mtd/Kconfig b/drivers/mtd/Kconfig index cf6d18da3527e..c77f537323ecb 100644 --- a/drivers/mtd/Kconfig +++ b/drivers/mtd/Kconfig @@ -339,6 +339,4 @@ source "drivers/mtd/spi-nor/Kconfig"

source "drivers/mtd/ubi/Kconfig"

-source "drivers/mtd/hisilicon/Kconfig" - endif # MTD diff --git a/drivers/mtd/Makefile b/drivers/mtd/Makefile index a6972d6b38103..93473d215a387 100644 --- a/drivers/mtd/Makefile +++ b/drivers/mtd/Makefile @@ -32,7 +32,7 @@ obj-$(CONFIG_MTD_SWAP) += mtdswap.o nftl-objs := nftlcore.o nftlmount.o inftl-objs := inftlcore.o inftlmount.o

-obj-y += chips/ lpddr/ maps/ devices/ nand/ tests/ hisilicon/ +obj-y += chips/ lpddr/ maps/ devices/ nand/ tests/

obj-$(CONFIG_MTD_SPI_NOR) += spi-nor/ obj-$(CONFIG_MTD_UBI) += ubi/ diff --git a/drivers/mtd/hisilicon/Kconfig b/drivers/mtd/hisilicon/Kconfig deleted file mode 100644 index 117c92d3547df..0000000000000 --- a/drivers/mtd/hisilicon/Kconfig +++ /dev/null @@ -1 +0,0 @@ -source "drivers/mtd/hisilicon/sfc/Kconfig" diff --git a/drivers/mtd/hisilicon/Makefile b/drivers/mtd/hisilicon/Makefile deleted file mode 100644 index 127b108941e3b..0000000000000 --- a/drivers/mtd/hisilicon/Makefile +++ /dev/null @@ -1 +0,0 @@ -obj-$(CONFIG_MTD_HISILICON_SFC) += sfc/ diff --git a/drivers/mtd/hisilicon/sfc/Kconfig b/drivers/mtd/hisilicon/sfc/Kconfig deleted file mode 100644 index 5bead1f871b66..0000000000000 --- a/drivers/mtd/hisilicon/sfc/Kconfig +++ /dev/null @@ -1,3 +0,0 @@ -config MTD_HISILICON_SFC - tristate - default m diff --git a/drivers/mtd/hisilicon/sfc/Makefile b/drivers/mtd/hisilicon/sfc/Makefile deleted file mode 100644 index 153825dc9983c..0000000000000 --- a/drivers/mtd/hisilicon/sfc/Makefile +++ /dev/null @@ -1,3 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0 -hi-sfc-objs := hrd_sfc_driver.o hrd_sflash_driver.o hrd_sflash_hal.o hrd_sflash_core.o -obj-$(CONFIG_MTD_HISILICON_SFC) += hi-sfc.o diff --git a/drivers/mtd/hisilicon/sfc/hrd_common.h b/drivers/mtd/hisilicon/sfc/hrd_common.h deleted file mode 100644 index 71dcaa98be16e..0000000000000 --- a/drivers/mtd/hisilicon/sfc/hrd_common.h +++ /dev/null @@ -1,106 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (C) 2019 Hisilicon Limited, All Rights Reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see <http: - */ - -#ifndef __HRD_COMMON_H__ -#define __HRD_COMMON_H__ - -#define HRD_OK (int)(0) -#define HRD_ERR (int)(-1) - -#define HRD_ERR_BASE (int)(-1024) - -#define HRD_COMMON_ERR_BASE (int)(HRD_ERR_BASE) -#define HRD_COMMON_ERR_NULL_POINTER (int)(HRD_COMMON_ERR_BASE - 1) -#define HRD_COMMON_ERR_UNKNOW_DEVICE (int)(HRD_COMMON_ERR_BASE - 2) -#define HRD_COMMON_ERR_UNKNOW_FUNCTION (int)(HRD_COMMON_ERR_BASE - 3) -#define HRD_COMMON_ERR_OPEN_FAIL (int)(HRD_COMMON_ERR_BASE - 4) -#define HRD_COMMON_ERR_READ_FAIL (int)(HRD_COMMON_ERR_BASE - 5) -#define HRD_COMMON_ERR_WRITE_FAIL (int)(HRD_COMMON_ERR_BASE - 6) -#define HRD_COMMON_ERR_MMAP_FAIL (int)(HRD_COMMON_ERR_BASE - 7) -#define HRD_COMMON_ERR_GET_MEN_RES_FAIL (int)(HRD_COMMON_ERR_BASE - 8) -#define HRD_COMMON_ERR_GET_IRQ_RES_FAIL (int)(HRD_COMMON_ERR_BASE - 9) -#define HRD_COMMON_ERR_INPUT_INVALID (int)(HRD_COMMON_ERR_BASE - 10) -#define HRD_COMMON_ERR_UNKNOW_MODE (int)(HRD_COMMON_ERR_BASE - 11) -#define HRD_COMMON_ERR_NOT_ENOUGH_RES (int)(HRD_COMMON_ERR_BASE - 12) -#define HRD_COMMON_ERR_RES_NOT_EXIST (int)(HRD_COMMON_ERR_BASE - 13) - -/* 16 bit nibble swap. example 0x1234 -> 0x2143 */ -#define HRD_NIBBLE_SWAP_16BIT(X) ((((X) & 0xf) << 4) | \ - (((X) & 0xF0) >> 4) | \ - (((X) & 0xF00) << 4) | \ - (((X) & 0xF000) >> 4)) - -/* 32 bit nibble swap. example 0x12345678 -> 0x21436587 */ -#define HRD_NIBBLE_SWAP_32BIT(X) ((((X) & 0xF) << 4) | \ - (((X) & 0xF0) >> 4) | \ - (((X) & 0xF00) << 4) | \ - (((X) & 0xF000) >> 4) | \ - (((X) & 0xF0000) << 4) | \ - (((X) & 0xF00000) >> 4) | \ - (((X) & 0xF000000) << 4) | \ - (((X) & 0xF0000000) >> 4)) - -/* 16 bit byte swap. example 0x1234->0x3412 */ -#define HRD_BYTE_SWAP_16BIT(X) ((((X) & 0xFF) << 8) | (((X) & 0xFF00) >> 8)) - -/* 32 bit byte swap. example 0x12345678->0x78563412 */ -#define HRD_BYTE_SWAP_32BIT(X) ((((X) & 0xFF) << 24) | \ - (((X) & 0xFF00) << 8) | \ - (((X) & 0xFF0000) >> 8) | \ - (((X) & 0xFF000000) >> 24)) - -/* 64 bit byte swap. example 0x11223344.55667788 -> 0x88776655.44332211 */ -#define HRD_BYTE_SWAP_64BIT(X) ((l64) ((((X) & 0xFFULL) << 56) | \ - (((X) & 0xFF00ULL) << 40) | \ - (((X) & 0xFF0000ULL) << 24) | \ - (((X) & 0xFF000000ULL) << 8) | \ - (((X) & 0xFF00000000ULL) >> 8) | \ - (((X) & 0xFF0000000000ULL) >> 24) | \ - (((X) & 0xFF000000000000ULL) >> 40) | \ - (((X) & 0xFF00000000000000ULL) >> 56))) - -/* -- Endianess macros. */ -#ifdef HRD_ENDNESS_BIGEND -#define HRD_16BIT_LE(X) HRD_BYTE_SWAP_16BIT(X) -#define HRD_32BIT_LE(X) HRD_BYTE_SWAP_32BIT(X) -#define HRD_64BIT_LE(X) HRD_BYTE_SWAP_64BIT(X) -#define HRD_16BIT_BE(X) (X) -#define HRD_32BIT_BE(X) (X) -#define HRD_64BIT_BE(X) (X) -#else -#define HRD_16BIT_LE(X) (X) -#define HRD_32BIT_LE(X) (X) -#define HRD_64BIT_LE(X) (X) -#define HRD_16BIT_BE(X) HRD_BYTE_SWAP_16BIT(X) -#define HRD_32BIT_BE(X) HRD_BYTE_SWAP_32BIT(X) -#define HRD_64BIT_BE(X) HRD_BYTE_SWAP_64BIT(X) -#endif - -#ifndef NULL -#define NULL ((void *)0) -#endif - -#define MTD_FLASH_MAP_DEBUG - -#ifdef MTD_FLASH_MAP_DEBUG -#define DB(x) x -#else -#define DB(x) -#endif - -#endif diff --git a/drivers/mtd/hisilicon/sfc/hrd_sfc_driver.c b/drivers/mtd/hisilicon/sfc/hrd_sfc_driver.c deleted file mode 100644 index 69fb1b306f0da..0000000000000 --- a/drivers/mtd/hisilicon/sfc/hrd_sfc_driver.c +++ /dev/null @@ -1,242 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (C) 2019 Hisilicon Limited, All Rights Reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -#include <linux/module.h> -#include <linux/types.h> -#include <linux/kernel.h> -#include <linux/init.h> -#include <linux/mtd/mtd.h> -#include <linux/mtd/map.h> -#include <linux/mtd/partitions.h> -#include <linux/platform_device.h> -#include <linux/acpi.h> -#include "hrd_common.h" -#include "hrd_sflash_driver.h" - -#define SFC_DRIVER_VERSION "1.9.60.0" - -static const char *g_sflashMtdList[] = {"sflash", NULL}; - -static unsigned int hrd_flash_info_fill(struct maps_init_info *maps, - struct resource *flash_iores, struct platform_device *pdev) -{ - u32 i; - - memset((void *)maps, 0x0, sizeof(struct maps_init_info)*MTD_MAX_FLASH_NUMBER); - - for (i = 0; i < MTD_MAX_FLASH_NUMBER; i++) { - maps[i].mtdDrv = g_sflashMtdList; - maps[i].mapInfo.name = pdev->name; - maps[i].mapInfo.phys = flash_iores->start; - maps[i].mapInfo.size = resource_size(flash_iores); - maps[i].mapInfo.bankwidth = 0x8; - DB(pr_info("[SFC] i is 0x%x, phys 0x%llx,size 0x%lx\n", - (u32) i, maps[i].mapInfo.phys, - maps[i].mapInfo.size)); - - DB(pr_info("[SFC] INFO: Found %s %d - base 0x%08x, size 0x%x\n", - maps[i].mapInfo.name, i, - (unsigned int)maps[i].mapInfo.phys, - (unsigned int)maps[i].mapInfo.size)); - } - - DB(pr_info("[SFC] INFO: %s - Found %d Flash Devices\n", __func__, i)); - return i; -} - -static int _hrd_flashProbe(const char **mtdDrv, struct map_info *map, - struct resource *sfc_regres, struct mtd_info **mtd) -{ - *mtd = NULL; - - for (; (!(*mtd) && *mtdDrv); mtdDrv++) { - DB(pr_info - ("[SFC] Using %s probe %s at addr 0x%llx,size 0x%x, width %dm\n", - *mtdDrv, map->name, (u64) map->phys, - (unsigned int)map->size, map->bankwidth)); - - *mtd = sflash_probe(map, sfc_regres); - if (*mtd) { - (*mtd)->owner = THIS_MODULE; - - if (mtd_device_register(*mtd, NULL, 0)) { - pr_err("probe: Failed to add the mtd device\n"); - iounmap((void *)map->virt); - map->virt = 0; - return -ENXIO; - } - - return HRD_OK; - } - DB(pr_info("[SFC] - Not detected\n")); - } - - return HRD_ERR; -} - -static int hrd_flashProbe(const char **mtdDrv, struct map_info *map, - struct resource *sfc_regres, struct mtd_info **mtd) -{ - int ret; - - if ((mtdDrv == NULL) - || (map == NULL) - || (mtd == NULL)) { - pr_err("[SFC] ERROR: NULL pointer parameter at %s entry\n", __func__); - return -EINVAL; - } - - map->virt = ioremap(map->phys, map->size); - if (!map->virt) { - pr_err("[SFC] Failed ioremap Flash device at base 0x%x.\n", - (unsigned int)map->phys); - return -EIO; - } - - DB(pr_info - ("[SFC] Io remapped ok.phy addr:0x%llx, virt addr:0x%llx\n", - (u64) map->phys, (u64) map->virt)); - - /* Skip bankwidths that are not supported */ - if (!map_bankwidth_supported(map->bankwidth)) { - pr_err("[SFC] ERROR: bankwidth %d not supported.\n", - (unsigned int)map->bankwidth); - iounmap((void *)map->virt); - return -EIO; - } - - ret = _hrd_flashProbe(mtdDrv, map, sfc_regres, mtd); - if (ret == HRD_OK) - return 0; - - iounmap((void *)map->virt); - map->virt = 0; - pr_err("[SFC] ERROR: %s - probe failed\n", __func__); - - return -ENXIO; -} - -static int flash_map_init(struct platform_device *pdev) -{ - u32 i; - u32 mapsNum; - struct device *dev = &pdev->dev; - struct resource *sfc_regres = NULL; - struct resource *flash_iores = NULL; - struct sfc_host *host = NULL; - - pr_info("SFC Driver\n"); - host = devm_kzalloc(dev, sizeof(struct sfc_host), GFP_KERNEL); - if (!host) { - pr_err("[SFC] ERROR: %s devm_kzalloc failed\n", __func__); - return -ENOMEM; - } - - sfc_regres = platform_get_resource(pdev, IORESOURCE_MEM, 0); - flash_iores = platform_get_resource(pdev, IORESOURCE_MEM, 1); - if (!sfc_regres || !flash_iores) - return -EFAULT; - - if (sfc_regres->end <= sfc_regres->start) { - pr_err("ERROR: sfc register error\n"); - return -EFAULT; - } - - if (flash_iores->end <= flash_iores->start) { - pr_err("[SFC] ERROR: flash addr error\n"); - return -EFAULT; - } - - mapsNum = hrd_flash_info_fill(host->maps, flash_iores, pdev); - DB(pr_info("[SFC] INFO: DEtected %d devices\n", mapsNum)); - - for (i = 0; i < mapsNum; i++) { - DB(pr_info("[SFC] MTD: Initialize the %s device at address 0x%08x\n", - host->maps[i].mapInfo.name, (unsigned int)host->maps[i].mapInfo.phys)); - - if (hrd_flashProbe - (host->maps[i].mtdDrv, &host->maps[i].mapInfo, sfc_regres, - &host->maps[i].mtdInfo) == 0) { - DB(pr_info("[SFC]- OK.\n")); - } else { - host->maps[i].mtdInfo = NULL; - DB(pr_err(" [SFC]- FAILED!\n")); - } - } - - host->mapsNum = mapsNum; - platform_set_drvdata(pdev, host); - - return 0; -} - -static void __exit flash_map_exit(struct platform_device *pdev) -{ - u32 i; - - struct sfc_host *host = platform_get_drvdata(pdev); - - for (i = 0; i < host->mapsNum; i++) { - if (host->maps[i].mtdInfo) - (void)mtd_device_unregister(host->maps[i].mtdInfo); - - if (host->maps[i].mapInfo.virt) { - iounmap((void *)host->maps[i].mapInfo.virt); - host->maps[i].mapInfo.virt = 0; - } - - if (host->maps[i].mtdInfo) - sflash_destroy(host->maps[i].mtdInfo); - } - -} - -static int hisi_sfc_probe(struct platform_device *pdev) -{ - return flash_map_init(pdev); -} - -static int hisi_sfc_remove(struct platform_device *pdev) -{ - flash_map_exit(pdev); - - return 0; -} - -static const struct acpi_device_id g_sfc_acpi_match[] = { - {"HISI0343", 0}, - {} -}; - -MODULE_DEVICE_TABLE(acpi, g_sfc_acpi_match); - -static struct platform_driver g_hisi_sfc_driver = { - .probe = hisi_sfc_probe, - .remove = hisi_sfc_remove, - .driver = { - .name = "hisi_sfc", - .acpi_match_table = ACPI_PTR(g_sfc_acpi_match), - }, -}; - -module_platform_driver(g_hisi_sfc_driver); - -MODULE_LICENSE("GPL v2"); -MODULE_AUTHOR("Huawei Tech. Co., Ltd."); -MODULE_DESCRIPTION("Hi16xx SFC driver"); -MODULE_VERSION(SFC_DRIVER_VERSION); - - diff --git a/drivers/mtd/hisilicon/sfc/hrd_sflash_core.c b/drivers/mtd/hisilicon/sfc/hrd_sflash_core.c deleted file mode 100644 index 68547d8e1d31b..0000000000000 --- a/drivers/mtd/hisilicon/sfc/hrd_sflash_core.c +++ /dev/null @@ -1,539 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (C) 2019 Hisilicon Limited, All Rights Reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -#include <linux/clk.h> -#include <linux/delay.h> -#include <linux/gpio.h> -#include <linux/interrupt.h> -#include <linux/kernel.h> -#include <linux/module.h> -#include <linux/of_gpio.h> -#include <linux/of_platform.h> -#include <linux/of_address.h> -#include <linux/platform_device.h> -#include <linux/resource.h> -#include <linux/signal.h> -#include <linux/types.h> -#include "hrd_common.h" -#include "hrd_sflash_spec.h" -#include "hrd_sflash_core.h" - -u32 SFC_RegisterRead(u64 reg_addr) -{ - u32 ulResult; - - ulResult = *(__iomem u32 *) (reg_addr); - - return HRD_32BIT_LE(ulResult); -} - -void SFC_RegisterWrite(u64 reg_addr, u32 ulValue) -{ - *(__iomem u32 *) (reg_addr) = HRD_32BIT_LE(ulValue); -} - -/* Judging sfc whether something is wrong */ -bool SFC_IsOpErr(u64 reg_addr) -{ - u32 IntStatus; - - IntStatus = SFC_RegisterRead(reg_addr + (u32) INTRAWSTATUS); - if ((IntStatus & SFC_OP_ERR_MASK) != 0) { - pr_err("%s ERROR: Int status=%x not cleared, clear\r\n", __func__, IntStatus); - SFC_RegisterWrite(reg_addr + INTCLEAR, INT_MASK); - return true; - } - - return false; -} - -s32 SFC_ClearInt(u64 reg_addr) -{ - u32 IntStatus; - - IntStatus = SFC_RegisterRead(reg_addr + (u32) INTRAWSTATUS); - if ((IntStatus & INT_MASK) != 0) { - pr_err("[SFC] [%s %d]: Int status=%x not cleared, clear\r\n", - __func__, __LINE__, IntStatus); - SFC_RegisterWrite(reg_addr + INTCLEAR, INT_MASK); - } - - return 0; -} - -s32 SFC_WaitInt(u64 reg_addr) -{ - u32 ulRegValue; - u32 ulCount = 0; - - ulRegValue = SFC_RegisterRead(reg_addr + (u32) INTRAWSTATUS); - while (((ulRegValue & CMD_OP_END_INT_BIT) != CMD_OP_END_INT_BIT) - && (ulCount < SFC_INT_WAIT_CNT)) { - udelay(1); - ulRegValue = SFC_RegisterRead(reg_addr + INTRAWSTATUS); - ulCount++; - } - - if (ulCount >= SFC_INT_WAIT_CNT) { - pr_err("[SFC] [%s %d]: wait int time out\n", __func__, __LINE__); - return WAIT_TIME_OUT; - } - - SFC_RegisterWrite(reg_addr + INTCLEAR, CMD_OP_END_INT_BIT); - - return HRD_OK; -} - -s32 SFC_WriteEnable(struct SFC_SFLASH_INFO *sflash) -{ - u32 ulRegValue; - - (void)SFC_ClearInt(sflash->sfc_reg_base); - SFC_RegisterWrite(sflash->sfc_reg_base + CMD_INS, sflash->sflash_dev_params.ucOpcodeWREN); - - ulRegValue = SFC_RegisterRead(sflash->sfc_reg_base + CMD_CONFIG); - ulRegValue &= (~(1 << ADDR_EN)) & (~(1 << DATA_EN)) & (~(1 << SEL_CS)); - ulRegValue |= (0x1 << LOCK_FLASH) | (SFC_CHIP_CS << SEL_CS) | (0x1 << START); - - wmb(); - - SFC_RegisterWrite(sflash->sfc_reg_base + CMD_CONFIG, ulRegValue); - - return SFC_WaitInt(sflash->sfc_reg_base); -} - -void SFC_FlashUnlock(struct SFC_SFLASH_INFO *sflash) -{ - u32 ulRegValue; - - ulRegValue = SFC_RegisterRead(sflash->sfc_reg_base + CMD_CONFIG); - ulRegValue &= (~(1 << LOCK_FLASH)); - wmb(); - SFC_RegisterWrite(sflash->sfc_reg_base + CMD_CONFIG, ulRegValue); -} - -u32 SFC_ReadStatus(struct SFC_SFLASH_INFO *sflash) -{ - u32 ulRegValue; - s32 ulRet; - - (void)SFC_ClearInt(sflash->sfc_reg_base); - - SFC_RegisterWrite(sflash->sfc_reg_base + CMD_INS, - sflash->sflash_dev_params.ucOpcodeRDSR); - - ulRegValue = SFC_RegisterRead(sflash->sfc_reg_base + CMD_CONFIG); - ulRegValue &= - (~(0xff << DATA_CNT)) & (~(0x1 << RW_DATA)) & (~(0x1 << SEL_CS)); - ulRegValue |= (0x3 << DATA_CNT) | (0x1 << RW_DATA) | (0x1 << DATA_EN) - | (SFC_CHIP_CS << SEL_CS) | (0x1 << START); - - wmb(); - SFC_RegisterWrite(sflash->sfc_reg_base + CMD_CONFIG, ulRegValue); - - ulRet = SFC_WaitInt(sflash->sfc_reg_base); - if (ulRet != HRD_OK) - return WAIT_TIME_OUT; - - ulRegValue = SFC_RegisterRead(sflash->sfc_reg_base + DATABUFFER1); - ulRegValue = ulRegValue & 0xff; - - return ulRegValue; -} - -s32 SFC_CheckBusy(struct SFC_SFLASH_INFO *sflash, u32 ulTimeOut) -{ - u32 ulRegValue; - u32 ulWaitCount = 0; - - ulRegValue = SFC_ReadStatus(sflash); - if (ulRegValue == WAIT_TIME_OUT) { - pr_err("[SFC] [%s %d]: SFC_ReadStatus time out\n", __func__, __LINE__); - return HRD_ERR; - } - - while (((ulRegValue & STATUS_REG_BUSY_BIT) == STATUS_REG_BUSY_BIT) - && (ulWaitCount < ulTimeOut)) { - udelay((unsigned long)1); - - ulRegValue = SFC_ReadStatus(sflash); - if (ulRegValue == WAIT_TIME_OUT) { - pr_err("[SFC] [%s %d]: SFC_ReadStatus time out\n", __func__, __LINE__); - return HRD_ERR; - } - - if ((sflash->manufacturerId == HISI_SPANSION_MANF_ID) - && (ulRegValue & (STATUS_REG_P_ERR | STATUS_REG_E_ERR))) { - pr_err("[SFC] [%s %d]: program err or erase err, status = %08x\n", - __func__, __LINE__, ulRegValue); - return HRD_ERR; - } - - ulWaitCount++; - if ((ulWaitCount > 0) && (ulWaitCount % 1000 == 0)) { /* Every cycle 1000 times, sleep 1 ms */ - msleep(1); - } - } - - if (ulWaitCount >= ulTimeOut) { - pr_err("[SFC] [%s %d]: CheckBusy time out\n", __func__, __LINE__); - return WAIT_TIME_OUT; - } - - return HRD_OK; -} - -s32 SFC_ClearStatus(struct SFC_SFLASH_INFO *sflash) -{ - u32 ulRegValue = 0; - s32 ulRet = HRD_ERR; - - (void)SFC_ClearInt(sflash->sfc_reg_base); - - if (sflash->manufacturerId == HISI_SPANSION_MANF_ID) { - /* 30 for spansion , clear status */ - SFC_RegisterWrite(sflash->sfc_reg_base + CMD_INS, 0x30); - - /* set configure reg and startup */ - ulRegValue = SFC_RegisterRead(sflash->sfc_reg_base + CMD_CONFIG); - - ulRegValue &= (~(1 << ADDR_EN)) & (~(1 << DATA_EN)) & (~(1 << SEL_CS)); - ulRegValue |= (SFC_CHIP_CS << SEL_CS) | (1 << START); - - wmb(); - - SFC_RegisterWrite(sflash->sfc_reg_base + CMD_CONFIG, ulRegValue); - - /* wait operate end */ - ulRet = SFC_WaitInt(sflash->sfc_reg_base); - if (ulRet != HRD_OK) - return ulRet; - } - - return HRD_OK; -} - -void SFC_CheckErr(struct SFC_SFLASH_INFO *sflash) -{ - u32 ulRegValue = 0; - unsigned long delay_us = 50; /* delay 50us */ - - if (sflash->manufacturerId == HISI_SPANSION_MANF_ID) { - ulRegValue = SFC_ReadStatus(sflash); - if (ulRegValue == WAIT_TIME_OUT) { - pr_err("[SFC] [%s %d]: SFC_ReadStatus time out\n", - __func__, __LINE__); - return; - } - - udelay(delay_us); - - if (ulRegValue & (STATUS_REG_P_ERR | STATUS_REG_E_ERR)) { - pr_err("[SFC] [%s %d]: program err or erase err, status = %08x\n", - __func__, __LINE__, ulRegValue); - - if (SFC_ClearStatus(sflash) != HRD_OK) { - pr_err("[SFC] [%s %d]: clear status failed\r\n", - __func__, __LINE__); - return; - } - - udelay(delay_us); - } - } -} - -s32 SFC_CheckCmdExcStatus(struct SFC_SFLASH_INFO *sflash) -{ - u32 temp; - u32 timeout = 1000; - - temp = SFC_RegisterRead(sflash->sfc_reg_base + CMD_CONFIG); - while (temp & 1) { - udelay(1); - temp = SFC_RegisterRead(sflash->sfc_reg_base + CMD_CONFIG); - timeout--; - - if (timeout == 0) { - pr_err("[SFC] %s (%d):Check cmd execute status time out!\n", __func__, __LINE__); - return HRD_ERR; - } - } - - return HRD_OK; -} - -int SFC_WaitFlashIdle(struct SFC_SFLASH_INFO *sflash) -{ - union UN_SFC_CMD_CONFIG temp; - u32 temp2 = 0; - u32 timeout = 10000; - int ret; - - temp.u32 = 0; - - (void)SFC_ClearInt(sflash->sfc_reg_base); - - SFC_RegisterWrite(sflash->sfc_reg_base + CMD_INS, SPI_CMD_RDSR); - do { - temp.bits.rw = SFC_CMD_CFG_READ; - temp.bits.addr_en = false; - temp.bits.data_en = true; - temp.bits.data_cnt = SFC_CMD_DATA_CNT(1); - temp.bits.sel_cs = SFC_CHIP_CS; - temp.bits.start = true; - SFC_RegisterWrite(sflash->sfc_reg_base + CMD_CONFIG, temp.u32); - - ret = SFC_CheckCmdExcStatus(sflash); - if (ret != HRD_OK) { - pr_err("[SFC] [%s %d]: cmd execute timeout\r\n", __func__, __LINE__); - return ret; - } - - udelay(80); /* Delay 80 subtleties */ - temp2 = SFC_RegisterRead(sflash->sfc_reg_base + DATABUFFER1); - if (!(temp2 & SPI_CMD_SR_WIP)) { - return HRD_OK; - } - - udelay(20); /* Delay 20 subtleties */ - } while (timeout--); - - pr_err("[SFC] [%s %d]: Write in progress!\r\n", __func__, __LINE__); - - return HRD_ERR; -} - -int SFC_GetDeviceId(struct SFC_SFLASH_INFO *sflash, u32 *id) -{ - int ret; - union UN_SFC_CMD_CONFIG temp; - - temp.u32 = 0; - - (void)SFC_ClearInt(sflash->sfc_reg_base); - - SFC_RegisterWrite(sflash->sfc_reg_base + CMD_INS, - SFLASH_DEFAULT_RDID_OPCD); - - temp.bits.rw = SFC_CMD_CFG_READ; - temp.bits.addr_en = false; - temp.bits.data_en = true; - temp.bits.data_cnt = SFC_CMD_DATA_CNT(1); - temp.bits.sel_cs = SFC_CHIP_CS; - temp.bits.start = true; - - wmb(); - SFC_RegisterWrite(sflash->sfc_reg_base + CMD_CONFIG, temp.u32); - - ret = SFC_CheckCmdExcStatus(sflash); - if (ret != HRD_OK) { - pr_err("[SFC] %s %d\n", __func__, __LINE__); - return ret; - } - - *id = SFC_RegisterRead(sflash->sfc_reg_base + DATABUFFER1); - pr_info("[SFC] %s(%d):get_device_id: 0x%x !\n", __func__, __LINE__, *id); - - return ret; -} - -s32 SFC_RegWordAlignRead(struct SFC_SFLASH_INFO *sflash, - u32 ulOffsetAddr, u32 *pulData, u32 ulReadLen) -{ - u32 i; - u32 ulDataCnt; - u32 ulRegValue; - s32 ulRet; - - if (!ulReadLen || ulReadLen > SFC_HARD_BUF_LEN || (ulReadLen & 0x3)) { - pr_err("[SFC] [%s %d]: len=%u err\n", __func__, __LINE__, ulReadLen); - return HRD_ERR; - } - - ulDataCnt = ulReadLen >> 0x2; - (void)SFC_ClearInt(sflash->sfc_reg_base); - - /* configure INS reg,send RDDATA operate */ - SFC_RegisterWrite(sflash->sfc_reg_base + CMD_INS, - sflash->sflash_dev_params.ucOpcodeREAD); - SFC_RegisterWrite(sflash->sfc_reg_base + CMD_ADDR, ulOffsetAddr); - - /* set configure reg and startup */ - ulRegValue = SFC_RegisterRead(sflash->sfc_reg_base + CMD_CONFIG); - ulRegValue &= (~(0xff << DATA_CNT) & (~(1 << SEL_CS))); - ulRegValue |= - ((ulReadLen - 1) << DATA_CNT) | (1 << ADDR_EN) | (1 << DATA_EN) | (1 << RW_DATA) - | (SFC_CHIP_CS << SEL_CS) | (0x1 << START); - - wmb(); - SFC_RegisterWrite(sflash->sfc_reg_base + CMD_CONFIG, ulRegValue); - - ulRet = SFC_WaitInt(sflash->sfc_reg_base); - if (ulRet != HRD_OK) { - pr_err("[SFC] [%s %d]: SFC_WaitInt fail\n", __func__, __LINE__); - return ulRet; - } - - if (SFC_IsOpErr(sflash->sfc_reg_base)) - return HRD_ERR; - - for (i = 0; i < ulDataCnt; i++) - pulData[i] = SFC_RegisterRead(sflash->sfc_reg_base + DATABUFFER1 + (u32)(0x4 * i)); - - return ulRet; -} - -s32 SFC_RegByteRead(struct SFC_SFLASH_INFO *sflash, - u32 ulOffsetAddr, u8 *pucData) -{ - u32 ulRegValue; - s32 ulRet; - - (void)SFC_ClearInt(sflash->sfc_reg_base); - - /* configure INS reg,send RDDATA operate */ - SFC_RegisterWrite(sflash->sfc_reg_base + CMD_INS, - sflash->sflash_dev_params.ucOpcodeREAD); - SFC_RegisterWrite(sflash->sfc_reg_base + CMD_ADDR, ulOffsetAddr); - - /* set configure reg and startup */ - ulRegValue = SFC_RegisterRead(sflash->sfc_reg_base + CMD_CONFIG); - ulRegValue &= (~(0xff << DATA_CNT) & (~(1 << SEL_CS))); - ulRegValue |= - (0 << DATA_CNT) | (1 << ADDR_EN) | (1 << DATA_EN) | (1 << RW_DATA) - | (SFC_CHIP_CS << SEL_CS) | (0x1 << START); - - wmb(); - SFC_RegisterWrite(sflash->sfc_reg_base + CMD_CONFIG, ulRegValue); - - ulRet = SFC_WaitInt(sflash->sfc_reg_base); - if (ulRet != HRD_OK) { - pr_err("[SFC] [%s %d]: SFC_WaitInt fail\n", __func__, __LINE__); - return ulRet; - } - - if (SFC_IsOpErr(sflash->sfc_reg_base)) - return HRD_ERR; - - *pucData = SFC_RegisterRead(sflash->sfc_reg_base + DATABUFFER1) & 0xff; - - return ulRet; -} - -/* 4bytes align, ulDataLen <=256 */ -s32 SFC_RegWordAlignWrite(struct SFC_SFLASH_INFO *sflash, - const u32 *ulData, u32 ulOffsetAddr, u32 ulWriteLen) -{ - u32 i; - u32 ulDataCnt; - u32 ulRegValue; - s32 ulRet; - - ulRet = SFC_WriteEnable(sflash); - if ((!ulWriteLen) || (ulWriteLen > SFC_HARD_BUF_LEN) || (ulWriteLen & 0x3)) { - pr_err("[SFC] [%s %d]: len=%u err\n", __func__, __LINE__, ulWriteLen); - ulRet = HRD_ERR; - goto rel; - } - - if (ulRet != HRD_OK) { - pr_err("[SFC] [%s %d]: SFC_WriteEnable fail\n", __func__, __LINE__); - goto rel; - } - - SFC_RegisterWrite(sflash->sfc_reg_base + CMD_INS, sflash->sflash_dev_params.ucOpcodePP); - - ulDataCnt = ulWriteLen >> 0x2; - for (i = 0; i < ulDataCnt; i++) { - SFC_RegisterWrite(sflash->sfc_reg_base + DATABUFFER1 + (u32)(0x4 * i), ulData[i]); - } - SFC_RegisterWrite(sflash->sfc_reg_base + CMD_ADDR, ulOffsetAddr); - - /* set configure reg and startup */ - ulRegValue = SFC_RegisterRead(sflash->sfc_reg_base + CMD_CONFIG); - ulRegValue &= - (~(0xff << DATA_CNT)) & (~(1 << RW_DATA) & (~(1 << SEL_CS))); - ulRegValue |= ((ulWriteLen - 1) << DATA_CNT) | (1 << ADDR_EN) | (1 << DATA_EN) - | (SFC_CHIP_CS << SEL_CS) | (0x1 << START); - - wmb(); - SFC_RegisterWrite(sflash->sfc_reg_base + CMD_CONFIG, ulRegValue); - ulRet = SFC_WaitInt(sflash->sfc_reg_base); - if (ulRet != HRD_OK) { - pr_err("[SFC] [%s %d]: SFC_WaitInt fail\n", __func__, __LINE__); - goto rel; - } - - if (SFC_IsOpErr(sflash->sfc_reg_base)) { - ulRet = HRD_ERR; - goto rel; - } - - SFC_RegisterWrite(sflash->sfc_reg_base + CMD_INS, - sflash->sflash_dev_params.ucOpcodeRDSR); - ulRet = SFC_CheckBusy(sflash, FLASH_WRITE_BUSY_WAIT_CNT); - - rel: - SFC_FlashUnlock(sflash); - - return ulRet; -} - -s32 SFC_RegByteWrite(struct SFC_SFLASH_INFO *sflash, - u8 ucData, u32 ulOffsetAddr) -{ - u32 ulRegValue; - s32 ulRet; - - ulRet = SFC_WriteEnable(sflash); - if (ulRet != HRD_OK) { - pr_err("[SFC] [%s %d]: SFC_WriteEnable failed\r\n", __func__, __LINE__); - goto rel; - } - - SFC_RegisterWrite(sflash->sfc_reg_base + CMD_INS, sflash->sflash_dev_params.ucOpcodePP); - SFC_RegisterWrite(sflash->sfc_reg_base + DATABUFFER1, ucData); - SFC_RegisterWrite(sflash->sfc_reg_base + CMD_ADDR, ulOffsetAddr); - - /* set configure reg and startup */ - ulRegValue = SFC_RegisterRead(sflash->sfc_reg_base + CMD_CONFIG); - ulRegValue &= - (~(0xff << DATA_CNT)) & (~(1 << RW_DATA)) & (~(1 << SEL_CS)); - ulRegValue |= (0 << DATA_CNT) | (1 << ADDR_EN) | (1 << DATA_EN) - | (SFC_CHIP_CS << SEL_CS) | (0x1 << START); - - wmb(); - SFC_RegisterWrite(sflash->sfc_reg_base + CMD_CONFIG, ulRegValue); - ulRet = SFC_WaitInt(sflash->sfc_reg_base); - if (ulRet != HRD_OK) { - pr_err("[SFC] [%s %d]: wait int failed\r\n", __func__, __LINE__); - goto rel; - } - - if (SFC_IsOpErr(sflash->sfc_reg_base)) { - ulRet = HRD_ERR; - goto rel; - } - - SFC_RegisterWrite(sflash->sfc_reg_base + CMD_INS, sflash->sflash_dev_params.ucOpcodeRDSR); - ulRet = SFC_CheckBusy(sflash, FLASH_WRITE_BUSY_WAIT_CNT); - - rel: - SFC_FlashUnlock(sflash); - - return ulRet; -} diff --git a/drivers/mtd/hisilicon/sfc/hrd_sflash_core.h b/drivers/mtd/hisilicon/sfc/hrd_sflash_core.h deleted file mode 100644 index ccf1d48334bdd..0000000000000 --- a/drivers/mtd/hisilicon/sfc/hrd_sflash_core.h +++ /dev/null @@ -1,160 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (C) 2019 Hisilicon Limited, All Rights Reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -#ifndef __HRD_SFLASH_CORE_H__ -#define __HRD_SFLASH_CORE_H__ - -#include "hrd_sflash_driver.h" - -#define SFC_HARD_BUF_LEN (256) -#define SPI_FLASH_PAGE_SIZE (256) - -#define SPI_CMD_SR_WIP 1 /* Write in Progress bit in status register position */ -#define SPI_CMD_RDSR 0x05 /* Read Status Register */ - -/* 3Byte or 4Byte addr */ -#define SPI_FLASH_3BYTE_ADDR (1) -#define SPI_FLASH_4BYTE_ADDR (1 << 1) - - /* Standard SPI */ -#define STANDARD_SPI_IF (1) - -/* Dual Input/Dual Output SPI */ -#define DUAL_IN_DUAL_OUT_SPI_IF (1 << 1) -/* Dual I/O SPI */ -#define DUAL_IO_SPI_IF (1 << 2) -/* Full Dual I/O SPI */ -#define FULL_DUAL_IO_SPI_IF (1 << 3) -/* Quad Input/Quad Output SPI */ -#define QUAD_IN_DUAL_OUT_SPI_IF (1 << 5) -/* Quad I/O SPI */ -#define QUAD_IO_SPI_IF (1 << 6) -/* Full Quad SPI */ -#define FULL_QUAD_IO_SPI_IF (1 << 7) - -#define SFC_CHIP_CS 0 -#define WAIT_TIME_OUT 0xFFFFFF -#define ERASE_WAIT_TIME 50 - -#define SFC_INT_WAIT_CNT 1000000 -#define FLASH_ERASE_BUSY_WAIT_CNT 1000000 -#define FLASH_WRITE_BUSY_WAIT_CNT 1000 - -#define STATUS_REG_P_ERR (1 << 6) -#define STATUS_REG_E_ERR (1 << 5) -#define STATUS_REG_BUSY_BIT 0x1 -#define FLASH_SIZE_CS_BIT(x) (8 * (x)) - -#define SFC_OP_ERR_MASK (0x1EC) - -/* SFC REG */ -#define GLOBAL_CONFIG (0x0100) -#define TIMING (0x0110) -#define INTRAWSTATUS (0x0120) -#define INTSTATUS (0x0124) -#define INTMASK (0x0128) -#define INTCLEAR (0x012C) -#define VERSION (0x01F8) -#define VERSION_SEL (0x01FC) -#define BUS_CONFIG1 (0x0200) -#define BUS_CONFIG2 (0x0204) -#define BUS_FLASH_SIZE (0x0210) -#define BUS_BASE_ADDR_CS0 (0x0214) -#define BUS_BASE_ADDR_CS1 (0x0218) -#define BUS_ALIAS_ADDR (0x021C) -#define BUS_ALIAS_CS (0x0220) -#define BUS_DMA_CTRL (0x0240) -#define BUS_DMA_MEM_SADDR (0x0244) -#define BUS_DMA_FLASH_SADDR (0x0248) -#define BUS_DMA_LEN (0x024C) -#define BUS_DMA_AHB_CTRL (0x0250) -#define CMD_CONFIG (0x0300) -#define CMD_INS (0x0308) -#define CMD_ADDR (0x030C) - -#define CMD_DATABUF(x) (0x0400 + 4 * ((x) - 1)) - -#define CONFIG BUS_CONFIG1 -#define CMD CMD_CONFIG -#define INS CMD_INS -#define ADDR CMD_ADDR -#define DATABUFFER1 CMD_DATABUF(1) -#define DATABUFFER2 CMD_DATABUF(2) -#define DATABUFFER3 CMD_DATABUF(3) -#define DATABUFFER4 CMD_DATABUF(4) -#define DATABUFFER5 CMD_DATABUF(5) -#define DATABUFFER6 CMD_DATABUF(6) -#define DATABUFFER7 CMD_DATABUF(7) -#define DATABUFFER8 CMD_DATABUF(8) - -/* INT */ -#define INT_MASK (0x1ff) -#define CMD_OP_END_INT_BIT (1) - -/* CMD_CONFIG */ -#define LOCK_FLASH 20 -#define MEM_TYPE 17 -#define DATA_CNT 9 -#define RW_DATA 8 /* 0 read 1 write */ -#define DATA_EN 7 -#define CMD_DUMMY 4 -#define ADDR_EN 3 -#define SEL_CS 1 -#define START 0 - -union UN_SFC_CMD_CONFIG { - struct { - unsigned int start:1; - unsigned int sel_cs:1; - unsigned int rsv0:1; - unsigned int addr_en:1; - unsigned int dummy_byte_cnt:3; - unsigned int data_en:1; -#define SFC_CMD_CFG_READ 1 -#define SFC_CMD_CFG_WRITE 0 - unsigned int rw:1; -#define SFC_CMD_DATA_CNT(x) ((x) - 1) - unsigned int data_cnt:8; - unsigned int mem_if_type:3; - unsigned int rsv1:12; - } bits; - unsigned int u32; -}; - -u32 SFC_RegisterRead(u64 reg_addr); -void SFC_RegisterWrite(u64 reg_addr, u32 ulValue); -s32 SFC_ClearInt(u64 reg_addr); -s32 SFC_WaitInt(u64 reg_addr); -bool SFC_IsOpErr(u64 reg_addr); -s32 SFC_WriteEnable(struct SFC_SFLASH_INFO *sflash); -void SFC_FlashUnlock(struct SFC_SFLASH_INFO *sflash); -u32 SFC_ReadStatus(struct SFC_SFLASH_INFO *sflash); -s32 SFC_CheckBusy(struct SFC_SFLASH_INFO *sflash, u32 ulTimeOut); -s32 SFC_ClearStatus(struct SFC_SFLASH_INFO *sflash); -void SFC_CheckErr(struct SFC_SFLASH_INFO *sflash); -s32 SFC_CheckCmdExcStatus(struct SFC_SFLASH_INFO *sflash); -int SFC_WaitFlashIdle(struct SFC_SFLASH_INFO *sflash); -int SFC_GetDeviceId(struct SFC_SFLASH_INFO *sflash, u32 *id); -s32 SFC_RegWordAlignRead(struct SFC_SFLASH_INFO *sflash, - u32 ulOffsetAddr, u32 *pulData, u32 ulReadLen); -s32 SFC_RegByteRead(struct SFC_SFLASH_INFO *sflash, - u32 ulOffsetAddr, u8 *pucData); -s32 SFC_RegWordAlignWrite(struct SFC_SFLASH_INFO *sflash, - const u32 *ulData, u32 ulOffsetAddr, u32 ulWriteLen); -s32 SFC_RegByteWrite(struct SFC_SFLASH_INFO *sflash, - u8 ucData, u32 ulOffsetAddr); - -#endif diff --git a/drivers/mtd/hisilicon/sfc/hrd_sflash_driver.c b/drivers/mtd/hisilicon/sfc/hrd_sflash_driver.c deleted file mode 100644 index 399c52481b9ad..0000000000000 --- a/drivers/mtd/hisilicon/sfc/hrd_sflash_driver.c +++ /dev/null @@ -1,390 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (C) 2019 Hisilicon Limited, All Rights Reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -#include <linux/kernel.h> -#include <linux/module.h> -#include <linux/types.h> -#include <linux/sched.h> -#include <linux/errno.h> -#include <linux/init.h> -#include <linux/blkdev.h> -#include <linux/console.h> -#include <linux/delay.h> -#include <linux/seq_file.h> -#include <linux/string.h> -#include <linux/slab.h> -#include <linux/device.h> -#include <linux/interrupt.h> -#include <linux/mtd/map.h> -#include <linux/mtd/mtd.h> -#include <linux/mutex.h> -#include <linux/version.h> -#include "hrd_common.h" -#include "hrd_sflash_driver.h" -#include "hrd_sflash_hal.h" - -#ifdef MTD_SFLASH_DEBUG -#define DB_LOCAL(x) x -#else -#define DB_LOCAL(x) -#endif - -#define SFLASH_SIZE_4K 0x1000 -#define SFLASH_SIZE_64K 0x10000 - -#define sflash_disable_irqs(flags, sflash_in_irq) \ - do { \ - sflash_in_irq = in_interrupt(); \ - if (!(sflash_in_irq)) \ - local_irq_save(flags); \ - } while (0) - -#define sflash_enable_irqs(flags, sflash_in_irq) \ - do { \ - if (!(sflash_in_irq)) \ - local_irq_restore(flags); \ - } while (0) - -static int sflash_read(struct mtd_info *mtd, loff_t from, size_t len, - size_t *retlen, u_char *buf); -static int sflash_write(struct mtd_info *mtd, loff_t from, size_t len, - size_t *retlen, const u_char *buf); -static int sflash_erase(struct mtd_info *mtd, struct erase_info *instr); -static void sflash_sync(struct mtd_info *mtd); -static int sflash_suspend(struct mtd_info *mtd); -static void sflash_resume(struct mtd_info *mtd); -static int sflash_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len); -static int sflash_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len); -static int sflash_block_isbad(struct mtd_info *mtd, loff_t ofs); -static int sflash_block_markbad(struct mtd_info *mtd, loff_t ofs); - -struct mtd_info *sflash_probe(struct map_info *map, struct resource *sfc_regres) -{ - struct mtd_info *mtd = NULL; - struct SFC_SFLASH_INFO *sflash = NULL; - unsigned long flags = 0; - unsigned long sflash_in_irq = 0; - - DB_LOCAL(pr_info("[SFC] INFO: entering %s\n", __func__)); - mtd = kmalloc(sizeof(*mtd), GFP_KERNEL); - if (!mtd) { - pr_err("ERROR: %s - Failed to allocate memory for mtd structure\n", __func__); - return NULL; - } - - sflash = kmalloc(sizeof(struct SFC_SFLASH_INFO), GFP_KERNEL); - if (!sflash) { - pr_err("[SFC] ERROR: %s - Failed to allocate memory for sflash structure\n", __func__); - kfree(mtd); - return NULL; - } - - memset(mtd, 0, sizeof(*mtd)); - memset(sflash, 0, sizeof(*sflash)); - - DB_LOCAL(pr_info("[SFC] INFO: %s - Base address %llx\n", __func__, map->phys)); - sflash->baseAddr = (u64) ioremap(map->phys, map->size); - if (!sflash->baseAddr) { - pr_err("[SFC] ERROR: %s - map flash error\n", __func__); - goto exit0; - } - - sflash->sfc_reg_base = (u64)ioremap_nocache(sfc_regres->start, resource_size(sfc_regres)); - - if (!sflash->sfc_reg_base) { - pr_err("[SFC] ERROR: %s - map register error\n", __func__); - goto exit1; - } - - mutex_init(&sflash->lock); - sflash->index = INVALID_DEVICE_NUMBER; - sflash_disable_irqs(flags, sflash_in_irq); - - if (hrd_sflash_init(sflash) != HRD_OK) { - sflash_enable_irqs(flags, sflash_in_irq); - pr_err("[SFC] ERROR: %s - Failed to initialize the SFlash.\n", __func__); - goto exit2; - } - - sflash_enable_irqs(flags, sflash_in_irq); - mtd->erasesize = sflash->sectorSize; - mtd->size = (u64) sflash->sectorSize * (u64) sflash->sectorNumber; - mtd->priv = map; - mtd->type = MTD_NORFLASH; - mtd->_erase = sflash_erase; - mtd->_read = sflash_read; - mtd->_write = sflash_write; - mtd->_sync = sflash_sync; - mtd->_suspend = sflash_suspend; - mtd->_resume = sflash_resume; - mtd->_lock = sflash_lock; - mtd->_unlock = sflash_unlock; - mtd->_block_isbad = sflash_block_isbad; - mtd->_block_markbad = sflash_block_markbad; - /* just like MTD_CAP_NORFLASH */ - mtd->flags = (MTD_WRITEABLE | MTD_BIT_WRITEABLE); - mtd->name = map->name; - mtd->writesize = 1; - - map->fldrv_priv = sflash; - - DB_LOCAL(pr_info("[SFC] INFO: %s - Detected SFlash device (size 0x%llx)\n", __func__, mtd->size)); - DB_LOCAL(pr_info("[SFC] Base Address : 0x%llx\n", sflash->baseAddr)); - DB_LOCAL(pr_info("[SFC] Manufacturer ID : 0x%02x\n", sflash->manufacturerId)); - DB_LOCAL(pr_info("[SFC] Device ID : 0x%04x\n", sflash->deviceId)); - DB_LOCAL(pr_info("[SFC] Sector Size : 0x%x\n", sflash->sectorSize)); - DB_LOCAL(pr_info("[SFC] Sector Number : %d\n", sflash->sectorNumber)); - - pr_info("[SFC] detected name:%s\n", sflash->sflash_dev_params.deviceModel); - - return mtd; - - exit0: - kfree(mtd); - kfree(sflash); - return NULL; - exit1: - iounmap((void *)sflash->baseAddr); - kfree(mtd); - kfree(sflash); - return NULL; - exit2: - iounmap((void *)sflash->baseAddr); - iounmap((void *)sflash->sfc_reg_base); - kfree(mtd); - kfree(sflash); - return NULL; -} - -void sflash_destroy(struct mtd_info *mtd) -{ - struct map_info *map = mtd->priv; - struct SFC_SFLASH_INFO *sflash = map->fldrv_priv; - - DB_LOCAL(pr_info("[SFC] INFO: %s called\n", __func__)); - - if (sflash->baseAddr != 0) - iounmap((void *)sflash->baseAddr); - - if (sflash->sfc_reg_base != 0) - iounmap((void *)sflash->sfc_reg_base); - - kfree(mtd); - kfree(sflash); -} - -static int sflash_read(struct mtd_info *mtd, loff_t from, size_t len, - size_t *retlen, u_char *buf) -{ - struct map_info *map = mtd->priv; - struct SFC_SFLASH_INFO *sflash = map->fldrv_priv; - u32 offset = ((u32) from); - int ret; - - *retlen = 0; - - DB_LOCAL(pr_info("[SFC] INFO: %s - offset %08x, len %d\n", __func__, offset, (int)len)); - - mutex_lock(&sflash->lock); - ret = SFC_RegModeRead(sflash, offset, (u8 *) buf, (u32) len); - if (ret != HRD_OK) { - mutex_unlock(&sflash->lock); - pr_err("[SFC] ERROR: %s - Failed to read block\n", __func__); - return -1; - } - - mutex_unlock(&sflash->lock); - *retlen = len; - - DB_LOCAL(pr_info(" [SFC] - OK\n")); - return 0; -} - -static int sflash_write(struct mtd_info *mtd, loff_t to, size_t len, - size_t *retlen, const u_char *buf) -{ - struct map_info *map = mtd->priv; - struct SFC_SFLASH_INFO *sflash = map->fldrv_priv; - u32 offset = ((u32) to); - int ret; - - *retlen = 0; - DB_LOCAL(pr_info("[SFC] INFO: %s-offset %08x, len %d\n", __func__, offset, (u32) len)); - - mutex_lock(&sflash->lock); - - ret = SFC_RegModeWrite(sflash, offset, buf, (u32) len); - if (ret != HRD_OK) { - mutex_unlock(&sflash->lock); - pr_err("[SFC] ERROR: %s - Failed to write block\n", __func__); - return -1; - } - - mutex_unlock(&sflash->lock); - - *retlen = len; - - DB_LOCAL(pr_info("[SFC] - OK")); - return 0; -} - -#define MIN(a, b) (((a) < (b)) ? (a) : (b)) - -static int sflash_erase(struct mtd_info *mtd, struct erase_info *instr) -{ - struct map_info *map = mtd->priv; - struct SFC_SFLASH_INFO *sflash = map->fldrv_priv; - u64 fsec, lsec; - u64 i; - - DB_LOCAL(pr_info("[SFC] INFO: %s - Addr %08llx, len %lld\n", __func__, instr->addr, instr->len)); - - if (!sflash) { - pr_err("[SFC] Error: sflash is NULL\n"); - return -EINVAL; - } - - if (instr->addr & (mtd->erasesize - 1)) { - pr_err("[SFC] Error: %s - Erase address not sector alligned\n", __func__); - return -EINVAL; - } - - if (instr->len & (mtd->erasesize - 1)) { - pr_err("[SFC] Error: %s - Erase length is not sector alligned\n", __func__); - return -EINVAL; - } - - if (instr->len + instr->addr > mtd->size) { - pr_err("[SFC] Error: %s - Erase exceeded flash size\n", __func__); - return -EINVAL; - } - - /* The start 64k of SPANSION flash can be erased only by using the 4k. */ - { - fsec = instr->addr; - do_div(fsec, SFLASH_SIZE_4K); - lsec = MIN(instr->addr + instr->len, SFLASH_SIZE_64K); - do_div(lsec, SFLASH_SIZE_4K); - - if (fsec < lsec) { - pr_info("[SFC] INFO: %s - for 4K from sector %lld to %lld\n", __func__, fsec, lsec - 1); - mutex_lock(&sflash->lock); - - SFC_CheckErr(sflash); - - for (i = fsec; i < lsec; i++) { - if (SFC_BlockErase(sflash, ((u32)i) * SFLASH_SIZE_4K, 0x20) != HRD_OK) { - mutex_unlock(&sflash->lock); - pr_err("[SFC] Error: %s - mvSFlashSectorErase on sector %lld\n", __func__, i); - return -1; - } - } - - mutex_unlock(&sflash->lock); - } - } - - fsec = instr->addr; - do_div(fsec, mtd->erasesize); - lsec = instr->len; - do_div(lsec, mtd->erasesize); - lsec = (fsec + lsec); - - DB_LOCAL(pr_info("[SFC] INFO: %s - from sector %u to %u\n", __func__, fsec, lsec - 1)); - - mutex_lock(&sflash->lock); - - for (i = fsec; i < lsec; i++) { - if (SFC_BlockErase(sflash, ((u32) i) * mtd->erasesize, 0) != HRD_OK) { - mutex_unlock(&sflash->lock); - pr_err("[SFC] Error: %s - mvSFlashSectorErase on sector %lld\n", __func__, i); -#if LINUX_VERSION_CODE > KERNEL_VERSION(4, 16, 0) - instr->fail_addr = ((u32) i) * mtd->erasesize; -#endif - - return -1; - } - } - - mutex_unlock(&sflash->lock); - -#if LINUX_VERSION_CODE < KERNEL_VERSION(4, 16, 0) - instr->state = MTD_ERASE_DONE; - mtd_erase_callback(instr); -#endif - - return 0; -} - -static int sflash_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len) -{ - int ret; - struct map_info *map = mtd->priv; - struct SFC_SFLASH_INFO *sflash = map->fldrv_priv; - - DB_LOCAL(pr_info("[SFC] INFO: %s called\n", __func__)); - - mutex_lock(&sflash->lock); - ret = SFC_WPSet(sflash, true); - mutex_unlock(&sflash->lock); - - return ret; -} - -static int sflash_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len) -{ - int ret; - struct map_info *map = mtd->priv; - struct SFC_SFLASH_INFO *sflash = map->fldrv_priv; - - pr_info("[SFC] INFO: %s called\n", __func__); - - mutex_lock(&sflash->lock); - ret = SFC_WPSet(sflash, false); - mutex_unlock(&sflash->lock); - - return ret; -} - -static void sflash_sync(struct mtd_info *mtd) -{ - DB_LOCAL(pr_info("[SFC] INFO: %s called - DUMMY\n", __func__)); -} - -static int sflash_suspend(struct mtd_info *mtd) -{ - DB_LOCAL(pr_info("[SFC] INFO: %s called - DUMMY()\n", __func__)); - return 0; -} - -static void sflash_resume(struct mtd_info *mtd) -{ - DB_LOCAL(pr_info("[SFC] INFO: %s called - DUMMY\n", __func__)); -} - -static int sflash_block_isbad(struct mtd_info *mtd, loff_t ofs) -{ - DB_LOCAL(pr_info("[SFC] INFO: %s called - DUMMY\n", __func__)); - return 0; -} - -static int sflash_block_markbad(struct mtd_info *mtd, loff_t ofs) -{ - DB_LOCAL(pr_info("[SFC] INFO: %s called - DUMMY\n", __func__)); - return 0; -} - - diff --git a/drivers/mtd/hisilicon/sfc/hrd_sflash_driver.h b/drivers/mtd/hisilicon/sfc/hrd_sflash_driver.h deleted file mode 100644 index f659758257847..0000000000000 --- a/drivers/mtd/hisilicon/sfc/hrd_sflash_driver.h +++ /dev/null @@ -1,105 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (C) 2019 Hisilicon Limited, All Rights Reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -#ifndef _HRD_SFLASH_DRIVER_H -#define _HRD_SFLASH_DRIVER_H - -#include <linux/mtd/map.h> - -#define INVALID_DEVICE_NUMBER 0xFFFFFFFF - -/* SFC cs num */ -#define SFC_CS_MAX_NUM 2 - -#define MTD_MAX_FLASH_NUMBER 1 - -/* SFC cs size 1GByte */ -#define SFC_CS_MAX_SIZE 0x40000000 - -#define HI_ARRAY_SIZE(a) ((sizeof(a)) / (sizeof(a[0]))) - -struct maps_init_info { - struct map_info mapInfo; - const char **mtdDrv; - struct mtd_info *mtdInfo; -}; - -struct sfc_host { - u32 mapsNum; - struct maps_init_info maps[MTD_MAX_FLASH_NUMBER]; -}; - -struct SPI_FLASH_DEVICE_PARAMS { - u8 ucOpcodeWREN; /* Write enable opcode */ - u8 ucOpcodeWRDI; /* Write disable opcode */ - u8 ucOpcodeRDID; /* Read ID opcode */ - u8 ucOpcodeRDSR; /* Read Status Register opcode */ - u8 ucOpcodeWRSR; /* Write Status register opcode */ - u8 ucOpcodeREAD; /* Read opcode */ - u8 ucOpcodeFSTRD; /* Fast Read opcode */ - u8 ucOpcodePP; /* Page program opcode */ - u8 ucOpcodeSSE; /* SubSector erase opcode */ - u8 ucOpcodeSE; /* Sector erase opcode */ - u8 ucOpcodeBE; /* Bulk erase opcode */ - u8 ucOpcodeRES; /* Read electronic signature */ - u8 ucOpcodePwrSave; /* Go into power save mode */ - u8 ucOpcodeRDVECR; /* Read Volatile Enhanced Configuration Reg */ - u8 ucOpcodeWRVECR; /* Write Volatile Enhanced Configuration Reg */ - u8 ucOpcodeEN4BAddr; /* Enter 4-byte address mode */ - u8 ucOpcodeEX4BAddr; /* Exit 4-byte address mode */ - u8 ucBusyFlagBit; - u8 ucReserve1; - u8 ucReserve2; - u32 ulSectorSize; /* Size of each sector */ - u32 ulBlockNumber; /* Number of blocks */ - u32 ulBlockSize; /* size of each block */ - const char *deviceModel; /* string with the device model */ - u32 ulManufacturerId; /* The manufacturer ID */ - u32 ulDeviceId; /* Device ID */ - u32 ulIdCFILen; /* ID-CFI Length - number bytes following */ - u32 ulPhySecArch; /* Physical Sector Architecture */ - u32 ulFId; /* Family ID */ - /* The MAX frequency that can be used with the device */ - u32 ulSpiMaxFreq; - /* The MAX frequency that can be used with the device for fast reads */ - u32 ulSpiMaxFastFreq; - /* Number of dumy bytes to read before real data when working in fast read mode. */ - u32 ulSpiFastRdDummyBytes; - u32 ulAddrModeSuport; /* it[1:0]:4/3Byte addr mode, 1:support */ - u32 ulIfTypeSuport; /* bit[6:0]:show 7 type, 1:supporu */ -}; - -struct SFC_SFLASH_INFO { - u64 baseAddr; /* Flash Base Address used in fast mode */ - u64 sfc_reg_base; /* sfc reg base addr */ - u32 space_size; - u8 manufacturerId; /* Manufacturer ID */ - u16 deviceId; /* Device ID */ - u32 sectorSize; /* Size of each sector - all the same */ - u32 sectorNumber; /* Number of sectors */ - u32 pageSize; /* Page size - affect allignment */ - /* index of the device in the sflash table (internal parameter) */ - u32 index; - u32 addr_mode; - u32 sfc_type_flag; - struct SPI_FLASH_DEVICE_PARAMS sflash_dev_params; - struct mutex lock; -}; - -extern struct mtd_info *sflash_probe(struct map_info *map, struct resource *sfc_regres); -extern void sflash_destroy(struct mtd_info *mtd); - -#endif /* _HRD_SLASH_DRIVER_H */ diff --git a/drivers/mtd/hisilicon/sfc/hrd_sflash_hal.c b/drivers/mtd/hisilicon/sfc/hrd_sflash_hal.c deleted file mode 100644 index 81fed47ec15e5..0000000000000 --- a/drivers/mtd/hisilicon/sfc/hrd_sflash_hal.c +++ /dev/null @@ -1,1159 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (C) 2019 Hisilicon Limited, All Rights Reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -#include <linux/clk.h> -#include <linux/delay.h> -#include <linux/gpio.h> -#include <linux/interrupt.h> -#include <linux/kernel.h> -#include <linux/module.h> -#include <linux/of_gpio.h> -#include <linux/of_platform.h> -#include <linux/of_address.h> -#include <linux/platform_device.h> -#include <linux/resource.h> -#include <linux/signal.h> -#include <linux/types.h> -#include "hrd_common.h" -#include "hrd_sflash_driver.h" -#include "hrd_sflash_core.h" -#include "hrd_sflash_spec.h" - -#define BIT0 (1<<0) -#define SPI_CMD_WRR 0x01 /* Write Register */ -#define SPI_CMD_CLSR 0x30 /* Clear Status Register */ - -struct SPI_FLASH_DEVICE_PARAMS g_stSPIFlashDevTable[] = { - /* NUMONYX N25Q128 SPI flash, 16MB, 256 sectors of 64K each */ - { - HISI_N25Q_WREN_CMND_OPCD, - HISI_N25Q_WRDI_CMND_OPCD, - HISI_N25Q_RDID_CMND_OPCD, - HISI_N25Q_RDSR_CMND_OPCD, - HISI_N25Q_WRSR_CMND_OPCD, - HISI_N25Q_READ_CMND_OPCD, - HISI_N25Q_FAST_RD_CMND_OPCD, - HISI_N25Q_PP_CMND_OPCD, - HISI_N25Q_SSE_CMND_OPCD, - HISI_N25Q_SE_CMND_OPCD, - HISI_N25Q_BE_CMND_OPCD, - HISI_SFLASH_NO_SPECIFIC_OPCD, - HISI_SFLASH_NO_SPECIFIC_OPCD, - HISI_N25Q_RDVECR_CMND_OPCD, - HISI_N25Q_WRVECR_CMND_OPCD, - HISI_N25Q_EN4BADDR_CMND_OPCD, - HISI_N25Q_EX4BADDR_CMND_OPCD, - HISI_N25Q_BUSY_FLAG_BIT, - 0, - 0, - HISI_N25Q128_PAGE_SIZE, - HISI_N25Q128_SECTOR_NUMBER, - HISI_N25Q128_SECTOR_SIZE, - "NUMONYX N25Q128", - HISI_N25Q128_MANF_ID, - HISI_N25Q128_DEVICE_ID, - 0xff, - 0xff, - 0xff, - HISI_N25Q128_MAX_SPI_FREQ, - HISI_N25Q128_MAX_FAST_SPI_FREQ, - HISI_N25Q128_FAST_READ_DUMMY_BYTES, - SPI_FLASH_3BYTE_ADDR, - STANDARD_SPI_IF}, - /* MIRCON MT25QU128AB SPI flash, 16MB, 256 sectors of 64K each */ - { - HISI_N25Q_WREN_CMND_OPCD, - HISI_N25Q_WRDI_CMND_OPCD, - HISI_N25Q_RDID_CMND_OPCD, - HISI_N25Q_RDSR_CMND_OPCD, - HISI_N25Q_WRSR_CMND_OPCD, - HISI_N25Q_READ_CMND_OPCD, - HISI_N25Q_FAST_RD_CMND_OPCD, - HISI_N25Q_PP_CMND_OPCD, - HISI_N25Q_SSE_CMND_OPCD, - HISI_N25Q_SE_CMND_OPCD, - HISI_N25Q_BE_CMND_OPCD, - HISI_SFLASH_NO_SPECIFIC_OPCD, - HISI_SFLASH_NO_SPECIFIC_OPCD, - HISI_N25Q_RDVECR_CMND_OPCD, - HISI_N25Q_WRVECR_CMND_OPCD, - HISI_N25Q_EN4BADDR_CMND_OPCD, - HISI_N25Q_EX4BADDR_CMND_OPCD, - HISI_N25Q_BUSY_FLAG_BIT, - 0, - 0, - HISI_N25Q128_PAGE_SIZE, - HISI_N25Q128_SECTOR_NUMBER, - HISI_N25Q128_SECTOR_SIZE, - "MIRCON MT25QU128AB", - HISI_N25Q128B_MANF_ID, - HISI_N25Q128B_DEVICE_ID, - 0xff, - 0xff, - 0xff, - HISI_N25Q128_MAX_SPI_FREQ, - HISI_N25Q128_MAX_FAST_SPI_FREQ, - HISI_N25Q128_FAST_READ_DUMMY_BYTES, - SPI_FLASH_3BYTE_ADDR, - STANDARD_SPI_IF}, - - /* NUMONYX N25Q256 SPI flash, 32MB, 256 sectors of 64K each */ - { - HISI_N25Q_WREN_CMND_OPCD, - HISI_N25Q_WRDI_CMND_OPCD, - HISI_N25Q_RDID_CMND_OPCD, - HISI_N25Q_RDSR_CMND_OPCD, - HISI_N25Q_WRSR_CMND_OPCD, - HISI_N25Q_READ_CMND_OPCD, - HISI_N25Q_FAST_RD_CMND_OPCD, - HISI_N25Q_PP_CMND_OPCD, - HISI_N25Q_SSE_CMND_OPCD, - HISI_N25Q_SE_CMND_OPCD, - HISI_N25Q_BE_CMND_OPCD, - HISI_SFLASH_NO_SPECIFIC_OPCD, - HISI_SFLASH_NO_SPECIFIC_OPCD, - HISI_N25Q_RDVECR_CMND_OPCD, - HISI_N25Q_WRVECR_CMND_OPCD, - HISI_N25Q_EN4BADDR_CMND_OPCD, - HISI_N25Q_EX4BADDR_CMND_OPCD, - HISI_N25Q_BUSY_FLAG_BIT, - 0, - 0, - HISI_N25Q256_PAGE_SIZE, - HISI_N25Q256_SECTOR_NUMBER, - HISI_N25Q256_SECTOR_SIZE, - "NUMONYX N25Q256", - HISI_N25Q256_MANF_ID, - HISI_N25Q256_DEVICE_ID, - 0xff, - 0xff, - 0xff, - HISI_N25Q256_MAX_SPI_FREQ, - HISI_N25Q256_MAX_FAST_SPI_FREQ, - HISI_N25Q256_FAST_READ_DUMMY_BYTES, - SPI_FLASH_3BYTE_ADDR, - STANDARD_SPI_IF}, - /* ST M25P80 SPI flash, 1MB, 16 sectors of 64K each */ - { - HISI_M25P_WREN_CMND_OPCD, - HISI_M25P_WRDI_CMND_OPCD, - HISI_M25P_RDID_CMND_OPCD, - HISI_M25P_RDSR_CMND_OPCD, - HISI_M25P_WRSR_CMND_OPCD, - HISI_M25P_READ_CMND_OPCD, - HISI_M25P_FAST_RD_CMND_OPCD, - HISI_M25P_PP_CMND_OPCD, - HISI_M25P_SSE_CMND_OPCD, - HISI_M25P_SE_CMND_OPCD, - HISI_M25P_BE_CMND_OPCD, - HISI_M25P_RES_CMND_OPCD, - HISI_SFLASH_NO_SPECIFIC_OPCD, /* power save not supported */ - HISI_SFLASH_UNKOWN_OPCD, /* next code need see datasheet */ - HISI_SFLASH_UNKOWN_OPCD, - HISI_SFLASH_UNKOWN_OPCD, - HISI_SFLASH_UNKOWN_OPCD, - HISI_SFLASH_UNKOWN_OPCD, - 0, - 0, - HISI_M25P_PAGE_SIZE, - HISI_M25P80_SECTOR_NUMBER, - HISI_M25P80_SECTOR_SIZE, - "ST M25P80", - HISI_M25PXXX_ST_MANF_ID, - HISI_M25P80_DEVICE_ID, - 0xff, - 0xff, - 0xff, - HISI_M25P80_MAX_SPI_FREQ, - HISI_M25P80_MAX_FAST_SPI_FREQ, - HISI_M25P80_FAST_READ_DUMMY_BYTES, - SPI_FLASH_3BYTE_ADDR, - STANDARD_SPI_IF}, - /* ST M25P32 SPI flash, 4MB, 64 sectors of 64K each */ - { - HISI_M25P_WREN_CMND_OPCD, - HISI_M25P_WRDI_CMND_OPCD, - HISI_M25P_RDID_CMND_OPCD, - HISI_M25P_RDSR_CMND_OPCD, - HISI_M25P_WRSR_CMND_OPCD, - HISI_M25P_READ_CMND_OPCD, - HISI_M25P_FAST_RD_CMND_OPCD, - HISI_M25P_PP_CMND_OPCD, - HISI_M25P_SSE_CMND_OPCD, - HISI_M25P_SE_CMND_OPCD, - HISI_M25P_BE_CMND_OPCD, - HISI_M25P_RES_CMND_OPCD, - HISI_SFLASH_NO_SPECIFIC_OPCD, /* power save not supported */ - HISI_SFLASH_UNKOWN_OPCD, /* next code need see datasheet */ - HISI_SFLASH_UNKOWN_OPCD, - HISI_SFLASH_UNKOWN_OPCD, - HISI_SFLASH_UNKOWN_OPCD, - HISI_SFLASH_UNKOWN_OPCD, - 0, - 0, - HISI_M25P_PAGE_SIZE, - HISI_M25P32_SECTOR_NUMBER, - HISI_M25P32_SECTOR_SIZE, - "ST M25P32", - HISI_M25PXXX_ST_MANF_ID, - HISI_M25P32_DEVICE_ID, - 0xff, - 0xff, - 0xff, - HISI_M25P32_MAX_SPI_FREQ, - HISI_M25P32_MAX_FAST_SPI_FREQ, - HISI_M25P32_FAST_READ_DUMMY_BYTES, - SPI_FLASH_3BYTE_ADDR, - STANDARD_SPI_IF}, - - /* ST M25P64 SPI flash, 8MB, 128 sectors of 64K each */ - { - HISI_M25P_WREN_CMND_OPCD, - HISI_M25P_WRDI_CMND_OPCD, - HISI_M25P_RDID_CMND_OPCD, - HISI_M25P_RDSR_CMND_OPCD, - HISI_M25P_WRSR_CMND_OPCD, - HISI_M25P_READ_CMND_OPCD, - HISI_M25P_FAST_RD_CMND_OPCD, - HISI_M25P_PP_CMND_OPCD, - HISI_M25P_SSE_CMND_OPCD, - HISI_M25P_SE_CMND_OPCD, - HISI_M25P_BE_CMND_OPCD, - HISI_M25P_RES_CMND_OPCD, - HISI_SFLASH_NO_SPECIFIC_OPCD, /* power save not supported */ - HISI_SFLASH_UNKOWN_OPCD, /* next code need see datasheet */ - HISI_SFLASH_UNKOWN_OPCD, - HISI_SFLASH_UNKOWN_OPCD, - HISI_SFLASH_UNKOWN_OPCD, - HISI_SFLASH_UNKOWN_OPCD, - 0, - 0, - HISI_M25P_PAGE_SIZE, - HISI_M25P64_SECTOR_NUMBER, - HISI_M25P64_SECTOR_SIZE, - "ST M25P64", - HISI_M25PXXX_ST_MANF_ID, - HISI_M25P64_DEVICE_ID, - 0xff, - 0xff, - 0xff, - HISI_M25P64_MAX_SPI_FREQ, - HISI_M25P64_MAX_FAST_SPI_FREQ, - HISI_M25P64_FAST_READ_DUMMY_BYTES, - SPI_FLASH_3BYTE_ADDR, - STANDARD_SPI_IF}, - /* ST M25P128 SPI flash, 16MB, 64 sectors of 256K each */ - { - HISI_M25P_WREN_CMND_OPCD, - HISI_M25P_WRDI_CMND_OPCD, - HISI_M25P_RDID_CMND_OPCD, - HISI_M25P_RDSR_CMND_OPCD, - HISI_M25P_WRSR_CMND_OPCD, - HISI_M25P_READ_CMND_OPCD, - HISI_M25P_FAST_RD_CMND_OPCD, - HISI_M25P_PP_CMND_OPCD, - HISI_M25P_SSE_CMND_OPCD, - HISI_M25P_SE_CMND_OPCD, - HISI_M25P_BE_CMND_OPCD, - HISI_M25P_RES_CMND_OPCD, - HISI_SFLASH_NO_SPECIFIC_OPCD, /* power save not supported */ - HISI_SFLASH_UNKOWN_OPCD, /* next code need see datasheet */ - HISI_SFLASH_UNKOWN_OPCD, - HISI_SFLASH_UNKOWN_OPCD, - HISI_SFLASH_UNKOWN_OPCD, - HISI_SFLASH_UNKOWN_OPCD, - 0, - 0, - HISI_M25P_PAGE_SIZE, - HISI_M25P128_SECTOR_NUMBER, - HISI_M25P128_SECTOR_SIZE, - "ST M25P128", - HISI_M25PXXX_ST_MANF_ID, - HISI_M25P128_DEVICE_ID, - 0xff, - 0xff, - 0xff, - HISI_M25P128_MAX_SPI_FREQ, - HISI_M25P128_MAX_FAST_SPI_FREQ, - HISI_M25P128_FAST_READ_DUMMY_BYTES, - SPI_FLASH_3BYTE_ADDR, - STANDARD_SPI_IF}, - /* Macronix MXIC MX25L6405 SPI flash, 8MB, 128 sectors of 64K each */ - { - HISI_MX25L_WREN_CMND_OPCD, - HISI_MX25L_WRDI_CMND_OPCD, - HISI_MX25L_RDID_CMND_OPCD, - HISI_MX25L_RDSR_CMND_OPCD, - HISI_MX25L_WRSR_CMND_OPCD, - HISI_MX25L_READ_CMND_OPCD, - HISI_MX25L_FAST_RD_CMND_OPCD, - HISI_MX25L_PP_CMND_OPCD, - HISI_MX25L_SSE_CMND_OPCD, - HISI_MX25L_SE_CMND_OPCD, - HISI_MX25L_BE_CMND_OPCD, - HISI_MX25L_RES_CMND_OPCD, - HISI_MX25L_DP_CMND_OPCD, - HISI_SFLASH_UNKOWN_OPCD, /* next code need see datasheet */ - HISI_SFLASH_UNKOWN_OPCD, - HISI_SFLASH_UNKOWN_OPCD, - HISI_SFLASH_UNKOWN_OPCD, - HISI_SFLASH_UNKOWN_OPCD, - 0, - 0, - HISI_MXIC_PAGE_SIZE, - HISI_MX25L6405_SECTOR_NUMBER, - HISI_MX25L6405_SECTOR_SIZE, - "MXIC MX25L6405", - HISI_MXIC_MANF_ID, - HISI_MX25L6405_DEVICE_ID, - 0xff, - 0xff, - 0xff, - HISI_MX25L6405_MAX_SPI_FREQ, - HISI_MX25L6405_MAX_FAST_SPI_FREQ, - HISI_MX25L6405_FAST_READ_DUMMY_BYTES, - SPI_FLASH_3BYTE_ADDR, - STANDARD_SPI_IF}, - /* Macronix MXIC MX25L1606E SPI flash, 2MB, 32 sectors of 64K each */ - { - HISI_MX25L_WREN_CMND_OPCD, - HISI_MX25L_WRDI_CMND_OPCD, - HISI_MX25L_RDID_CMND_OPCD, - HISI_MX25L_RDSR_CMND_OPCD, - HISI_MX25L_WRSR_CMND_OPCD, - HISI_MX25L_READ_CMND_OPCD, - HISI_MX25L_FAST_RD_CMND_OPCD, - HISI_MX25L_PP_CMND_OPCD, - HISI_MX25L_SSE_CMND_OPCD, - HISI_MX25L_SE_CMND_OPCD, - HISI_MX25L_BE_CMND_OPCD, - HISI_MX25L_RES_CMND_OPCD, - HISI_MX25L_DP_CMND_OPCD, - HISI_SFLASH_NO_SPECIFIC_OPCD, /* can't support next 5 code */ - HISI_SFLASH_NO_SPECIFIC_OPCD, - HISI_SFLASH_NO_SPECIFIC_OPCD, - HISI_SFLASH_NO_SPECIFIC_OPCD, - HISI_SFLASH_NO_SPECIFIC_OPCD, - 0, - 0, - HISI_MXIC_PAGE_SIZE, - HISI_MX25L1606E_SECTOR_NUMBER, - HISI_MX25L1606E_SECTOR_SIZE, - "MXIC MX25L1606E", - HISI_MXIC_MANF_ID, - HISI_MX25L1606E_DEVICE_ID, - 0xff, - 0xff, - 0xff, - HISI_MX25L1606E_MAX_SPI_FREQ, - HISI_MX25L1606E_MAX_FAST_SPI_FREQ, - HISI_MX25L1606E_FAST_READ_DUMMY_BYTES, - SPI_FLASH_3BYTE_ADDR, - STANDARD_SPI_IF}, - /* Macronix MXIC MX25U12835F SPI flash, 16MB, 255 sectors of 64K each */ - { - HISI_MX25U12835F_WREN_CMND_OPCD, - HISI_MX25U12835F_WRDI_CMND_OPCD, - HISI_MX25U12835F_RDID_CMND_OPCD, - HISI_MX25U12835F_RDSR_CMND_OPCD, - HISI_MX25U12835F_WRSR_CMND_OPCD, - HISI_MX25U12835F_READ_CMND_OPCD, - HISI_MX25U12835F_FAST_RD_CMND_OPCD, - HISI_MX25U12835F_PP_CMND_OPCD, - HISI_MX25U12835F_SSE_CMND_OPCD, - HISI_MX25U12835F_SE_CMND_OPCD, - HISI_MX25U12835F_BE_CMND_OPCD, - HISI_MX25U12835F_RES_CMND_OPCD, - HISI_MX25U12835F_DP_CMND_OPCD, - HISI_SFLASH_NO_SPECIFIC_OPCD, /* can't support next 5 code */ - HISI_SFLASH_NO_SPECIFIC_OPCD, - HISI_SFLASH_NO_SPECIFIC_OPCD, - HISI_SFLASH_NO_SPECIFIC_OPCD, - HISI_SFLASH_NO_SPECIFIC_OPCD, - 0, - 0, - HISI_MX25U12835F_PAGE_SIZE, - HISI_MX25U12835F_SECTOR_NUMBER, - HISI_MX25U12835F_SECTOR_SIZE, - "MXIC MX25U12835F", - HISI_MX25U12835F_MANF_ID, - HISI_MX25U12835F_DEVICE_ID, - 0xff, - 0xff, - 0xff, - HISI_MX25U12835F_MAX_SPI_FREQ, - HISI_MX25U12835F_MAX_FAST_SPI_FREQ, - HISI_MX25U12835F_FAST_READ_DUMMY_BYTES, - SPI_FLASH_3BYTE_ADDR, - STANDARD_SPI_IF}, - /* SPANSION S25FL128P SPI flash, 16MB, 64 sectors of 256K each */ - { - HISI_S25FL_WREN_CMND_OPCD, - HISI_S25FL_WRDI_CMND_OPCD, - HISI_S25FL_RDID_CMND_OPCD, - HISI_S25FL_RDSR_CMND_OPCD, - HISI_S25FL_WRSR_CMND_OPCD, - HISI_S25FL_READ_CMND_OPCD, - HISI_S25FL_FAST_RD_CMND_OPCD, - HISI_S25FL_PP_CMND_OPCD, - HISI_S25FL_SSE_CMND_OPCD, - HISI_S25FL_SE_CMND_OPCD, - HISI_S25FL_BE_CMND_OPCD, - HISI_S25FL_RES_CMND_OPCD, - HISI_S25FL_DP_CMND_OPCD, - HISI_SFLASH_UNKOWN_OPCD, /* next code need see datasheet */ - HISI_SFLASH_UNKOWN_OPCD, - HISI_SFLASH_UNKOWN_OPCD, - HISI_SFLASH_UNKOWN_OPCD, - HISI_SFLASH_UNKOWN_OPCD, - 0, - 0, - HISI_S25FL_PAGE_SIZE, - HISI_S25FL128_SECTOR_NUMBER, - HISI_S25FL128_SECTOR_SIZE, - "SPANSION S25FL128", - HISI_SPANSION_MANF_ID, - HISI_S25FL128_DEVICE_ID, - 0xff, - 0xff, - 0x80, - HISI_S25FL128_MAX_SPI_FREQ, - HISI_M25P128_MAX_FAST_SPI_FREQ, - HISI_M25P128_FAST_READ_DUMMY_BYTES, - SPI_FLASH_3BYTE_ADDR, - STANDARD_SPI_IF}, - /* SPANSION S25FS128S SPI flash, 16MB, 255 sectors of 64K each + */ - { - HISI_S25FL_WREN_CMND_OPCD, - HISI_S25FL_WRDI_CMND_OPCD, - HISI_S25FL_RDID_CMND_OPCD, - HISI_S25FL_RDSR_CMND_OPCD, - HISI_S25FL_WRSR_CMND_OPCD, - HISI_S25FL_READ_CMND_OPCD, - HISI_S25FL_FAST_RD_CMND_OPCD, - HISI_S25FL_PP_CMND_OPCD, - HISI_S25FL_SSE_CMND_OPCD, - HISI_S25FL_SE_CMND_OPCD, - HISI_S25FL_BE_CMND_OPCD, - HISI_S25FL_RES_CMND_OPCD, - HISI_S25FL_DP_CMND_OPCD, - HISI_SFLASH_UNKOWN_OPCD, /* next code need see datasheet */ - HISI_SFLASH_UNKOWN_OPCD, - HISI_SFLASH_UNKOWN_OPCD, - HISI_SFLASH_UNKOWN_OPCD, - HISI_SFLASH_UNKOWN_OPCD, - 0, - 0, - HISI_S25FL_PAGE_SIZE, - HISI_S25FL128_SECTOR_NUMBER, - HISI_S25FL128_SECTOR_SIZE, - "SPANSION S25FS128", - HISI_SPANSION_MANF_ID, - HISI_S25FL128_DEVICE_ID, - 0xff, - 0xff, - 0x81, - HISI_S25FL128_MAX_SPI_FREQ, - HISI_M25P128_MAX_FAST_SPI_FREQ, - HISI_M25P128_FAST_READ_DUMMY_BYTES, - SPI_FLASH_3BYTE_ADDR, - STANDARD_SPI_IF}, - /* ATMEL AT25DF641 SPI flash, 8MB, 128 sectors of 64K each */ - { - HISI_AT25DF_WREN_CMND_OPCD, - HISI_AT25DF_WRDI_CMND_OPCD, - HISI_AT25DF_RDID_CMND_OPCD, - HISI_AT25DF_RDSR_CMND_OPCD, - HISI_AT25DF_WRSR_CMND_OPCD, - HISI_AT25DF_READ_CMND_OPCD, - HISI_AT25DF_FAST_RD_CMND_OPCD, - HISI_AT25DF_PP_CMND_OPCD, - HISI_AT25DF_SSE_CMND_OPCD, - HISI_AT25DF_SE_CMND_OPCD, - HISI_AT25DF_BE_CMND_OPCD, - HISI_AT25DF_RES_CMND_OPCD, - HISI_SFLASH_NO_SPECIFIC_OPCD, /* power save not supported */ - HISI_SFLASH_UNKOWN_OPCD, /* next code need see datasheet */ - HISI_SFLASH_UNKOWN_OPCD, - HISI_SFLASH_UNKOWN_OPCD, - HISI_SFLASH_UNKOWN_OPCD, - HISI_SFLASH_UNKOWN_OPCD, - 0, - 0, - HISI_AT25DF_PAGE_SIZE, - HISI_AT25DF641_SECTOR_NUMBER, - HISI_AT25DF641_SECTOR_SIZE, - "AT 25DF641", - HISI_AT25DFXXX_AT_MANF_ID, - HISI_AT25DF641_DEVICE_ID, - 0xff, - 0xff, - 0xff, - HISI_AT25DF641_MAX_SPI_FREQ, - HISI_AT25DF641_MAX_FAST_SPI_FREQ, - HISI_AT25DF641_FAST_READ_DUMMY_BYTES, - SPI_FLASH_3BYTE_ADDR, - STANDARD_SPI_IF}, - - /* MIRCON DEFAULT */ - { - HISI_N25Q_WREN_CMND_OPCD, - HISI_N25Q_WRDI_CMND_OPCD, - HISI_N25Q_RDID_CMND_OPCD, - HISI_N25Q_RDSR_CMND_OPCD, - HISI_N25Q_WRSR_CMND_OPCD, - HISI_N25Q_READ_CMND_OPCD, - HISI_N25Q_FAST_RD_CMND_OPCD, - HISI_N25Q_PP_CMND_OPCD, - HISI_N25Q_SSE_CMND_OPCD, - HISI_N25Q_SE_CMND_OPCD, - HISI_N25Q_BE_CMND_OPCD, - HISI_SFLASH_NO_SPECIFIC_OPCD, - HISI_SFLASH_NO_SPECIFIC_OPCD, - HISI_N25Q_RDVECR_CMND_OPCD, - HISI_N25Q_WRVECR_CMND_OPCD, - HISI_N25Q_EN4BADDR_CMND_OPCD, - HISI_N25Q_EX4BADDR_CMND_OPCD, - HISI_N25Q_BUSY_FLAG_BIT, - 0, - 0, - HISI_N25Q128_PAGE_SIZE, - HISI_N25Q128_SECTOR_NUMBER, - HISI_N25Q128_SECTOR_SIZE, - "MIRCON DEFAULT", - HISI_N25Q128B_MANF_ID, - 0xffff, - 0xff, - 0xff, - 0xff, - HISI_N25Q128_MAX_SPI_FREQ, - HISI_N25Q128_MAX_FAST_SPI_FREQ, - HISI_N25Q128_FAST_READ_DUMMY_BYTES, - SPI_FLASH_3BYTE_ADDR, - STANDARD_SPI_IF}, - - /* MIXC DEFAULT */ - { - HISI_MX25U12835F_WREN_CMND_OPCD, - HISI_MX25U12835F_WRDI_CMND_OPCD, - HISI_MX25U12835F_RDID_CMND_OPCD, - HISI_MX25U12835F_RDSR_CMND_OPCD, - HISI_MX25U12835F_WRSR_CMND_OPCD, - HISI_MX25U12835F_READ_CMND_OPCD, - HISI_MX25U12835F_FAST_RD_CMND_OPCD, - HISI_MX25U12835F_PP_CMND_OPCD, - HISI_MX25U12835F_SSE_CMND_OPCD, - HISI_MX25U12835F_SE_CMND_OPCD, - HISI_MX25U12835F_BE_CMND_OPCD, - HISI_MX25U12835F_RES_CMND_OPCD, - HISI_MX25U12835F_DP_CMND_OPCD, - HISI_SFLASH_NO_SPECIFIC_OPCD, - HISI_SFLASH_NO_SPECIFIC_OPCD, - HISI_SFLASH_NO_SPECIFIC_OPCD, - HISI_SFLASH_NO_SPECIFIC_OPCD, - HISI_SFLASH_NO_SPECIFIC_OPCD, - 0, - 0, - HISI_MX25U12835F_PAGE_SIZE, - HISI_MX25U12835F_SECTOR_NUMBER, - HISI_MX25U12835F_SECTOR_SIZE, - "MIXC DEFAULT", - HISI_MX25U12835F_MANF_ID, - 0xffff, - 0xff, - 0xff, - 0xff, - HISI_MX25U12835F_MAX_SPI_FREQ, - HISI_MX25U12835F_MAX_FAST_SPI_FREQ, - HISI_MX25U12835F_FAST_READ_DUMMY_BYTES, - SPI_FLASH_3BYTE_ADDR, - STANDARD_SPI_IF}, - - /* SPANSION DEFAULT */ - { - HISI_S25FL_WREN_CMND_OPCD, - HISI_S25FL_WRDI_CMND_OPCD, - HISI_S25FL_RDID_CMND_OPCD, - HISI_S25FL_RDSR_CMND_OPCD, - HISI_S25FL_WRSR_CMND_OPCD, - HISI_S25FL_READ_CMND_OPCD, - HISI_S25FL_FAST_RD_CMND_OPCD, - HISI_S25FL_PP_CMND_OPCD, - HISI_S25FL_SSE_CMND_OPCD, - HISI_S25FL_SE_CMND_OPCD, - HISI_S25FL_BE_CMND_OPCD, - HISI_S25FL_RES_CMND_OPCD, - HISI_S25FL_DP_CMND_OPCD, - HISI_SFLASH_UNKOWN_OPCD, - HISI_SFLASH_UNKOWN_OPCD, - HISI_SFLASH_UNKOWN_OPCD, - HISI_SFLASH_UNKOWN_OPCD, - HISI_SFLASH_UNKOWN_OPCD, - 0, - 0, - HISI_S25FL_PAGE_SIZE, - HISI_S25FL128_SECTOR_NUMBER, - HISI_S25FL128_SECTOR_SIZE, - "SPANSION DEFAULT", - HISI_SPANSION_MANF_ID, - 0xffff, - 0xff, - 0xff, - 0xff, - HISI_S25FL128_MAX_SPI_FREQ, - HISI_M25P128_MAX_FAST_SPI_FREQ, - HISI_M25P128_FAST_READ_DUMMY_BYTES, - SPI_FLASH_3BYTE_ADDR, - STANDARD_SPI_IF}, - - /* DEFAULT */ - { - HISI_MX25U12835F_WREN_CMND_OPCD, - HISI_MX25U12835F_WRDI_CMND_OPCD, - HISI_MX25U12835F_RDID_CMND_OPCD, - HISI_MX25U12835F_RDSR_CMND_OPCD, - HISI_MX25U12835F_WRSR_CMND_OPCD, - HISI_MX25U12835F_READ_CMND_OPCD, - HISI_MX25U12835F_FAST_RD_CMND_OPCD, - HISI_MX25U12835F_PP_CMND_OPCD, - HISI_MX25U12835F_SSE_CMND_OPCD, - HISI_MX25U12835F_SE_CMND_OPCD, - HISI_MX25U12835F_BE_CMND_OPCD, - HISI_MX25U12835F_RES_CMND_OPCD, - HISI_MX25U12835F_DP_CMND_OPCD, - HISI_SFLASH_NO_SPECIFIC_OPCD, - HISI_SFLASH_NO_SPECIFIC_OPCD, - HISI_SFLASH_NO_SPECIFIC_OPCD, - HISI_SFLASH_NO_SPECIFIC_OPCD, - HISI_SFLASH_NO_SPECIFIC_OPCD, - 0, - 0, - HISI_MX25U12835F_PAGE_SIZE, - HISI_MX25U12835F_SECTOR_NUMBER, - HISI_MX25U12835F_SECTOR_SIZE, - "DEFAULT", - 0xff, - 0xffff, - 0xff, - 0xff, - 0xff, - HISI_MX25U12835F_MAX_SPI_FREQ, - HISI_MX25U12835F_MAX_FAST_SPI_FREQ, - HISI_MX25U12835F_FAST_READ_DUMMY_BYTES, - SPI_FLASH_3BYTE_ADDR, - STANDARD_SPI_IF} -}; - -s32 SFC_BlockErase(struct SFC_SFLASH_INFO *sflash, u32 ulAddr, u32 ErCmd) -{ - u32 ulRegValue; - s32 ulRet; - - ulRet = SFC_WriteEnable(sflash); - if (ulRet != HRD_OK) { - pr_err("[%s %d]: SFC_WriteEnable fail\n", __func__, __LINE__); - goto rel; - } - - SFC_RegisterWrite(sflash->sfc_reg_base + CMD_INS, - ErCmd ? ErCmd : sflash->sflash_dev_params.ucOpcodeSE); - SFC_RegisterWrite(sflash->sfc_reg_base + CMD_ADDR, ulAddr); - - /* set configure reg and startup */ - ulRegValue = SFC_RegisterRead(sflash->sfc_reg_base + CMD_CONFIG); - ulRegValue &= (~(1 << DATA_EN) & (~(1 << SEL_CS))); - ulRegValue |= ((SFC_CHIP_CS << SEL_CS) | (1 << START) | (1 << ADDR_EN)); - - wmb(); - - SFC_RegisterWrite(sflash->sfc_reg_base + CMD_CONFIG, ulRegValue); - ulRet = SFC_WaitInt(sflash->sfc_reg_base); - if (ulRet != HRD_OK) { - pr_err("[SFC] [%s %d]: SFC_WaitInt fail\n", __func__, __LINE__); - goto rel; - } - - if (SFC_IsOpErr(sflash->sfc_reg_base)) { - ulRet = HRD_ERR; - goto rel; - } - - ulRet = SFC_CheckBusy(sflash, FLASH_ERASE_BUSY_WAIT_CNT); - if (ulRet != HRD_OK) { - pr_err("[SFC] [%s %d]: SFC_CheckBusy fail\n", __func__, __LINE__); - goto rel; - } - - rel: - SFC_FlashUnlock(sflash); - return ulRet; -} - -static s32 _SFC_RegModeWrite(struct SFC_SFLASH_INFO *sflash, - u32 offset, const u8 *pucSrc, u32 ulWriteLen) -{ - u32 i; - s32 slRet; - u32 ulRemain; - u32 ulAlignLen; - - ulRemain = ulWriteLen % SFC_HARD_BUF_LEN; - ulAlignLen = ulWriteLen - ulRemain; - - for (i = 0; i < ulAlignLen; i += SFC_HARD_BUF_LEN) { - slRet = SFC_RegWordAlignWrite(sflash, (const u32 *)(pucSrc + i), offset + i, SFC_HARD_BUF_LEN); - if (slRet != HRD_OK) { - pr_err("[SFC] [%s %d]: SFC_RegWordWrite fail\n", __func__, __LINE__); - return slRet; - } - - if ((i > 0) && (i % 8192 == 0)) { /* After write 8192 bytes of data, sleep 1 ms. */ - msleep(1); - } - } - - if (ulRemain >= 0x4) { - slRet = SFC_RegWordAlignWrite(sflash, (const u32 *)(pucSrc + i), offset + i, ulRemain & (~0x3)); - if (slRet != HRD_OK) { - pr_err("[SFC] [%s %d]: SFC_RegWordAlignWrite fail\n", __func__, __LINE__); - return slRet; - } - i += ulRemain & (~0x3); - } - - for (; i < ulWriteLen; i++) { - slRet = SFC_RegByteWrite(sflash, *(const u8 *)(pucSrc + i), offset + i); - if (slRet != HRD_OK) { - pr_err("[SFC] [%s %d]: SFC_RegByteWrite fail\n", __func__, __LINE__); - return slRet; - } - } - - return HRD_OK; -} - -s32 SFC_RegModeWrite(struct SFC_SFLASH_INFO *sflash, - u32 offset, const u8 *pucSrc, u32 ulWriteLen) -{ - s32 slRet; - u32 ulPageRemain; - u32 offsetTmp = offset; - u8 *pucSrcTmp = (u8 *)pucSrc; - - if (!pucSrc) { - pr_err("[SFC] [%s %d]: Pointer is null\n", __func__, __LINE__); - return HRD_COMMON_ERR_NULL_POINTER; - } - - if (ulWriteLen > sflash->space_size) { - pr_err("[SFC] [%s %d]: ulReadLen is invalid\n", __func__, __LINE__); - return HRD_COMMON_ERR_INPUT_INVALID; - } - - SFC_CheckErr(sflash); - - /* the size of data remaining on the first page */ - ulPageRemain = SPI_FLASH_PAGE_SIZE - (offset % SPI_FLASH_PAGE_SIZE); - if (ulWriteLen >= ulPageRemain) { - slRet = _SFC_RegModeWrite(sflash, offsetTmp, pucSrcTmp, ulPageRemain); - if (slRet != HRD_OK) - return slRet; - - offsetTmp += ulPageRemain; - pucSrcTmp += ulPageRemain; - ulWriteLen -= ulPageRemain; - } - - if (ulWriteLen) { - slRet = _SFC_RegModeWrite(sflash, offsetTmp, pucSrcTmp, ulWriteLen); - if (slRet != HRD_OK) - return slRet; - } - - if (SFC_IsOpErr(sflash->sfc_reg_base)) - return HRD_ERR; - - return HRD_OK; -} - -s32 SFC_RegModeRead(struct SFC_SFLASH_INFO *sflash, - u32 offset, u8 *pucDest, u32 ulReadLen) -{ - u32 i; - u32 ulRemain; - u32 ulAlignLen; - s32 ret = HRD_OK; - - if (!sflash || !pucDest) { - pr_err("[SFC] [%s %d]: Pointer is null\n", __func__, __LINE__); - return HRD_COMMON_ERR_NULL_POINTER; - } - - if (ulReadLen > sflash->space_size) { - pr_err("[SFC] [%s %d]: ulReadLen is invalid\n", __func__, __LINE__); - return HRD_COMMON_ERR_INPUT_INVALID; - } - - SFC_CheckErr(sflash); - - ulRemain = ulReadLen % SFC_HARD_BUF_LEN; - ulAlignLen = ulReadLen - ulRemain; - - for (i = 0; i < ulAlignLen; i += SFC_HARD_BUF_LEN) { - ret = SFC_RegWordAlignRead(sflash, offset + i, (u32 *) (pucDest + i), SFC_HARD_BUF_LEN); - if (ret != HRD_OK) { - pr_err("[SFC] [%s %d]: SFC_RegWordAlignRead fail\n", __func__, __LINE__); - return ret; - } - } - - if (ulRemain >= 0x4) { - ret = SFC_RegWordAlignRead(sflash, offset + i, (u32 *) (pucDest + i), ulRemain & (~0x3)); - if (ret != HRD_OK) { - pr_err("[SFC] [%s %d]: SFC_RegWordAlignRead fail\n", __func__, __LINE__); - return ret; - } - i += ulRemain & (~0x3); - } - - for (; i < ulReadLen; i++) { - ret = SFC_RegByteRead(sflash, offset + i, pucDest + i); - if (ret != HRD_OK) { - pr_err("[SFC] [%s %d]: SFC_RegByteRead fail\n", __func__, __LINE__); - return ret; - } - } - - return ret; -} - -static s32 SFC_SPIFlashIdGet(struct SFC_SFLASH_INFO *pFlinfo, - u8 *pulManuId, u16 *pulDevId, u8 *pcfi_len, u8 *psec_arch, u8 *pfid) -{ - u8 ulID0; - u16 ulID1; - u16 ulID2; - s32 ulRet; - u32 ulRegValue; - u32 readid_cmd; - - if (!pulManuId || !pulDevId) { - pr_err("[SFC] [%s %d]: input params is invalid\n", __func__, __LINE__); - return HRD_COMMON_ERR_NULL_POINTER; - } - - (void)SFC_ClearInt(pFlinfo->sfc_reg_base); - - if (pFlinfo->index >= HI_ARRAY_SIZE(g_stSPIFlashDevTable)) - readid_cmd = SFLASH_DEFAULT_RDID_OPCD; - else - readid_cmd = g_stSPIFlashDevTable[pFlinfo->index].ucOpcodeRDID; - - SFC_RegisterWrite(pFlinfo->sfc_reg_base + CMD_INS, readid_cmd); - - ulRegValue = SFC_RegisterRead(pFlinfo->sfc_reg_base + CMD_CONFIG); - ulRegValue &= (~(0xff << DATA_CNT)) & (~(1 << RW_DATA)) - & (~(1 << SEL_CS)) & (~(1 << ADDR_EN)); - ulRegValue |= (0x5 << DATA_CNT) | (0x1 << RW_DATA) | (0x1 << DATA_EN) - | (SFC_CHIP_CS << SEL_CS) | (0x1 << START); - - wmb(); - SFC_RegisterWrite(pFlinfo->sfc_reg_base + CMD_CONFIG, ulRegValue); - ulRet = SFC_WaitInt(pFlinfo->sfc_reg_base); - if (ulRet != HRD_OK) { - pr_err("[SFC] [%s %d]: wait int failed\r\n", __func__, __LINE__); - return WAIT_TIME_OUT; - } - - ulRet = SFC_CheckCmdExcStatus(pFlinfo); - if (ulRet) { - pr_err("[SFC] [%s %d]: cmd execute timeout\r\n", __func__, __LINE__); - return WAIT_TIME_OUT; - } - - ulRegValue = SFC_RegisterRead(pFlinfo->sfc_reg_base + DATABUFFER1); - - ulID0 = ulRegValue & 0xff; - ulID1 = (ulRegValue >> 0x8) & 0xff; - ulID2 = (ulRegValue >> 0x10) & 0xff; - - *pulManuId = ulID0; - *pulDevId = (u16) (ulID1 << 0x8) | ulID2; - *pcfi_len = (ulRegValue >> 0x18) & 0xff; - - ulRegValue = SFC_RegisterRead(pFlinfo->sfc_reg_base + DATABUFFER2); - *psec_arch = ulRegValue & 0xff; - *pfid = (ulRegValue >> 0x8) & 0xff; - - pr_info("[SFC] [%s %d]:ulManuId=0x%x, ulDevId=0x%x cfi_len=0x%x, sec_arch=0x%x, fid=0x%x\n", - __func__, __LINE__, *pulManuId, *pulDevId, *pcfi_len, *psec_arch, *pfid); - - return HRD_OK; -} - -static int MirconWPSet(struct SFC_SFLASH_INFO *sflash, bool val) -{ - int ret; - - ret = SFC_WriteEnable(sflash); - if (ret != HRD_OK) { - pr_err("SFC_WriteEnable fail\n"); - return ret; - } - - if (val) - SFC_RegisterWrite(sflash->sfc_reg_base + DATABUFFER1, 0xDC); - else - SFC_RegisterWrite(sflash->sfc_reg_base + DATABUFFER1, 0x0); - - SFC_RegisterWrite(sflash->sfc_reg_base + CMD_INS, SPI_CMD_WRR); - SFC_RegisterWrite(sflash->sfc_reg_base + CMD_CONFIG, 0x81); - udelay((unsigned long)10); /* Delay 10 subtleties */ - - return ret; -} - -static int SpansionWPSet(struct SFC_SFLASH_INFO *sflash, bool val) -{ - int ret; - - ret = SFC_WriteEnable(sflash); - if (ret != HRD_OK) { - pr_err("SFC_WriteEnable fail\n"); - return ret; - } - - if (val) { - SFC_RegisterWrite(sflash->sfc_reg_base + DATABUFFER1, 0x9C); - SFC_RegisterWrite(sflash->sfc_reg_base + CMD_INS, SPI_CMD_WRR); - SFC_RegisterWrite(sflash->sfc_reg_base + CMD_CONFIG, 0x81); - } else { - SFC_RegisterWrite(sflash->sfc_reg_base + CMD_INS, SPI_CMD_CLSR); - SFC_RegisterWrite(sflash->sfc_reg_base + CMD_CONFIG, 0x1); - udelay(50); /* Delay 50 subtleties */ - ret = SFC_CheckCmdExcStatus(sflash); - if (ret != HRD_OK) { - pr_err("[SFC] [%s %d]: SFC_CheckCmdExcStatus fail\n", __func__, __LINE__); - return ret; - } - - udelay(50); /* Delay 50 subtleties */ - ret = SFC_WaitFlashIdle(sflash); - if (ret != HRD_OK) { - pr_err("[SFC] [%s %d]: SFC_WaitFlashIdle fail\n", __func__, __LINE__); - return ret; - } - - udelay(200); /* Delay 200 subtleties */ - ret = SFC_WriteEnable(sflash); - if (ret != HRD_OK) { - pr_err("[SFC] [%s %d]: SFC_WriteEnable fail\n", __func__, __LINE__); - return ret; - } - - udelay(50); /* Delay 50 subtleties */ - SFC_RegisterWrite(sflash->sfc_reg_base + DATABUFFER1, 0); - SFC_RegisterWrite(sflash->sfc_reg_base + CMD_INS, SPI_CMD_WRR); - SFC_RegisterWrite(sflash->sfc_reg_base + CMD_CONFIG, 0x81); - } - - return ret; -} - -static int MxicWPSet(struct SFC_SFLASH_INFO *sflash, bool val) -{ - u32 status; - int ret; - - ret = SFC_WriteEnable(sflash); - if (ret != HRD_OK) { - pr_err("SFC_WriteEnable fail\n"); - return ret; - } - - /* status register[7:0] : bit7[SRWD], bit6[QE], bit5~bit2[BP3 ~ BP0], bit1[WEL], bit0[WIP] */ - status = SFC_ReadStatus(sflash); - if (status == WAIT_TIME_OUT) { - ret = HRD_ERR; - pr_err("[SFC] [%s %d]: SFC_ReadStatus time out\n", __func__, __LINE__); - return ret; - } - - if (((status >> 1) & 0x1) != 1) { - ret = HRD_ERR; - pr_err("[SFC] [%s %d]: Write enable fail\n", __func__, __LINE__); - return ret; - } - - if (val) { - status |= 0x3c; - status &= (~(u32) 0x2); - SFC_RegisterWrite(sflash->sfc_reg_base + DATABUFFER1, status); - SFC_RegisterWrite(sflash->sfc_reg_base + CMD_INS, SPI_CMD_WRR); - SFC_RegisterWrite(sflash->sfc_reg_base + CMD_CONFIG, 0x81); - } else { - status = status & (~(u32) 0x3c); - status = status & (~(u32) 0x2); - SFC_RegisterWrite(sflash->sfc_reg_base + DATABUFFER1, status); - SFC_RegisterWrite(sflash->sfc_reg_base + CMD_INS, SPI_CMD_WRR); - SFC_RegisterWrite(sflash->sfc_reg_base + CMD_CONFIG, 0x81); - } - - ret = SFC_WaitInt(sflash->sfc_reg_base); - if (ret != HRD_OK) - return ret; - - return ret; -} - -int SFC_WPSet(struct SFC_SFLASH_INFO *sflash, bool val) -{ - u32 device_id; - int ret; - - (void)SFC_ClearInt(sflash->sfc_reg_base); - - SFC_CheckErr(sflash); - - /* First try to read the Manufacturer and Device IDs */ - ret = SFC_GetDeviceId(sflash, &device_id); - if (ret != HRD_OK) { - pr_err("[SFC][%s %d]: Failed to get the device id\n", __func__, __LINE__); - return ret; - } - - sflash->manufacturerId = device_id; - ret = SFC_WaitFlashIdle(sflash); - if (ret != HRD_OK) { - pr_err("[SFC][%s %d]: SFC_WaitFlashIdle fail\n", __func__, __LINE__); - return ret; - } - - /* WP will lock sfc */ - if (HISI_M25PXXX_ST_MANF_ID == (u8) (device_id)) { - ret = MirconWPSet(sflash, val); - } else if (HISI_SPANSION_MANF_ID == (u8) (device_id)) { - ret = SpansionWPSet(sflash, val); - } else if (HISI_MX25U12835F_MANF_ID == (u8) (device_id)) { - ret = MxicWPSet(sflash, val); - /* default */ - } else { - ret = MxicWPSet(sflash, val); - } - - if (ret != HRD_OK) - goto done; - - udelay(10); /* delay 10 us */ - - ret = SFC_CheckCmdExcStatus(sflash); - if (ret != HRD_OK) { - pr_err("[SFC] [%s %d]: SFC_CheckCmdExcStatus fail\n", __func__, __LINE__); - goto done; - } - - ret = SFC_WaitFlashIdle(sflash); - if (ret != HRD_OK) { - pr_err("[SFC] [%s %d]: SFC_WaitFlashIdle fail\n", __func__, __LINE__); - goto done; - } - -done: - SFC_FlashUnlock(sflash); - return ret; -} - -#define CMP_MANF_ID(indx, id) \ - ((g_stSPIFlashDevTable[indx].ulManufacturerId != 0xff) ? (g_stSPIFlashDevTable[indx].ulManufacturerId == (id)) : 1) - -#define CMP_DEVICE_ID(indx, id) \ - ((g_stSPIFlashDevTable[indx].ulDeviceId != 0xffff) ? (g_stSPIFlashDevTable[indx].ulDeviceId == (id)) : 1) - -#define CMP_EXTERN_ID(indx, cfi_len, sec_arch, fid) \ - (((g_stSPIFlashDevTable[indx].ulIdCFILen != 0xff) ? (g_stSPIFlashDevTable[indx].ulIdCFILen == (cfi_len)) : 1) && \ - ((g_stSPIFlashDevTable[indx].ulPhySecArch != 0xff) ? (g_stSPIFlashDevTable[indx].ulPhySecArch == (sec_arch)) : 1) && \ - ((g_stSPIFlashDevTable[indx].ulFId != 0xff) ? (g_stSPIFlashDevTable[indx].ulFId == (fid)) : 1)) - -static bool SFC_IsFlashIdErr(u8 manf, u16 dev) -{ - if (((manf == 0xFF) && (dev == 0xFFFF)) - || ((manf == 0x0) && (dev == 0x0))) { - return true; - } - - return false; -} - -int hrd_sflash_init(struct SFC_SFLASH_INFO *pFlinfo) -{ - int ret; - u8 manf; - u16 dev; - u8 cfi_len; - u8 sec_arch; - u8 fid; - u32 indx; - bool detectFlag = false; - - /* check for NULL pointer */ - if (pFlinfo == NULL) { - pr_err("[SFC] %s HRD_ERR: Null pointer parameter!\n", __func__); - return HRD_COMMON_ERR_INPUT_INVALID; - } - - /* First try to read the Manufacturer and Device IDs */ - ret = SFC_SPIFlashIdGet(pFlinfo, &manf, &dev, &cfi_len, &sec_arch, &fid); - if (ret != HRD_OK) { - pr_err("[SFC] %s HRD_ERR: Failed to get the SFlash ID!\n", __func__); - return ret; - } - - if (SFC_IsFlashIdErr(manf, dev)) { - pr_err("flash id err, manf=0x%x,dev=0x%x\n", manf, dev); - return HRD_ERR; - } - - /* loop over the whole table and look for the appropriate SFLASH */ - for (indx = 0; indx < HI_ARRAY_SIZE(g_stSPIFlashDevTable); indx++) { - if ((CMP_MANF_ID(indx, manf)) - && (CMP_DEVICE_ID(indx, dev)) - && (CMP_EXTERN_ID(indx, cfi_len, sec_arch, fid))) { - pFlinfo->manufacturerId = manf; - pFlinfo->deviceId = dev; - pFlinfo->index = indx; - pFlinfo->addr_mode = g_stSPIFlashDevTable[indx].ulAddrModeSuport; - pFlinfo->sfc_type_flag = g_stSPIFlashDevTable[indx].ulIfTypeSuport; - detectFlag = true; - break; - } - } - - if (!detectFlag) { - pr_err("[SFC] %s HRD_ERR: manf:0x%x, dev:0x%x, Unknown SPI flash device!\n", __func__, manf, dev); - return HRD_ERR; - } - - /* fill the info based on the model detected */ - pFlinfo->sectorSize = g_stSPIFlashDevTable[pFlinfo->index].ulBlockSize; - pFlinfo->sectorNumber = g_stSPIFlashDevTable[pFlinfo->index].ulBlockNumber; - pFlinfo->pageSize = g_stSPIFlashDevTable[pFlinfo->index].ulSectorSize; - pFlinfo->space_size = pFlinfo->sectorSize * pFlinfo->sectorNumber; - memcpy(&pFlinfo->sflash_dev_params, - &g_stSPIFlashDevTable[pFlinfo->index], - sizeof(struct SPI_FLASH_DEVICE_PARAMS)); - - return ret; -} diff --git a/drivers/mtd/hisilicon/sfc/hrd_sflash_hal.h b/drivers/mtd/hisilicon/sfc/hrd_sflash_hal.h deleted file mode 100644 index f612731d06cd4..0000000000000 --- a/drivers/mtd/hisilicon/sfc/hrd_sflash_hal.h +++ /dev/null @@ -1,31 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (C) 2019 Hisilicon Limited, All Rights Reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -#ifndef __HRD_SFLASH_HAL_H__ -#define __HRD_SFLASH_HAL_H__ -#include "hrd_sflash_driver.h" - -extern void SFC_CheckErr(struct SFC_SFLASH_INFO *sflash); -extern s32 SFC_RegModeRead(struct SFC_SFLASH_INFO *sflash, u32 offset, - u8 *pucDest, u32 ulReadLen); -extern s32 SFC_RegModeWrite(struct SFC_SFLASH_INFO *sflash, u32 offset, - const u8 *pucSrc, u32 ulWriteLen); -extern s32 SFC_BlockErase(struct SFC_SFLASH_INFO *sflash, u32 ulAddr, - u32 ErCmd); -extern int hrd_sflash_init(struct SFC_SFLASH_INFO *pFlinfo); -extern int SFC_WPSet(struct SFC_SFLASH_INFO *sflash, bool val); - -#endif diff --git a/drivers/mtd/hisilicon/sfc/hrd_sflash_spec.h b/drivers/mtd/hisilicon/sfc/hrd_sflash_spec.h deleted file mode 100644 index 151957d62d351..0000000000000 --- a/drivers/mtd/hisilicon/sfc/hrd_sflash_spec.h +++ /dev/null @@ -1,376 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (C) 2019 Hisilicon Limited, All Rights Reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -#ifndef __HRD_SFLASH_SPEC_H__ -#define __HRD_SFLASH_SPEC_H__ - -#define SFLASH_DEFAULT_RDID_OPCD 0x9F /* Default Read ID */ -#define SFLASH_DEFAULT_WREN_OPCD 0x06 /* Default Write Enable */ - -/* Constants */ -#define HISI_SFLASH_READ_CMND_LENGTH 4 /* 1B opcode + 3B address */ -#define HISI_SFLASH_SE_CMND_LENGTH 4 /* 1B opcode + 3B address */ -#define HISI_SFLASH_BE_CMND_LENGTH 1 /* 1B opcode */ -#define HISI_SFLASH_PP_CMND_LENGTH 4 /* 1B opcode + 3B address */ -#define HISI_SFLASH_WREN_CMND_LENGTH 1 /* 1B opcode */ -#define HISI_SFLASH_WRDI_CMND_LENGTH 1 /* 1B opcode */ -#define HISI_SFLASH_RDID_CMND_LENGTH 1 /* 1B opcode */ -/* 1B manf ID and 2B device ID */ -#define HISI_SFLASH_RDID_REPLY_LENGTH 3 -#define HISI_SFLASH_RDSR_CMND_LENGTH 1 /* 1B opcode */ -#define HISI_SFLASH_RDSR_REPLY_LENGTH 1 /* 1B status */ -/* 1B opcode + 1B status value */ -#define HISI_SFLASH_WRSR_CMND_LENGTH 2 -#define HISI_SFLASH_DP_CMND_LENGTH 1 /* 1B opcode */ -#define HISI_SFLASH_RES_CMND_LENGTH 1 /* 1B opcode */ - -/* Status Register Bit Masks */ -/* bit 0; write in progress */ -#define HISI_SFLASH_STATUS_REG_WIP_OFFSET 0 -/* bit 2-4; write protect option */ -#define HISI_SFLASH_STATUS_REG_WP_OFFSET 2 -/* bit 7; lock status register write */ -#define HISI_SFLASH_STATUS_REG_SRWD_OFFSET 7 -#define HISI_SFLASH_STATUS_REG_WIP_MASK \ - (0x1 << HISI_SFLASH_STATUS_REG_WIP_OFFSET) -#define HISI_SFLASH_STATUS_REG_SRWD_MASK \ - (0x1 << HISI_SFLASH_STATUS_REG_SRWD_OFFSET) - -#define HISI_SFLASH_MAX_WAIT_LOOP 1000000 -#define HISI_SFLASH_CHIP_ERASE_MAX_WAIT_LOOP 0x50000000 - -#define HISI_SFLASH_DEFAULT_RDID_OPCD 0x9F /* Default Read ID */ -#define HISI_SFLASH_DEFAULT_WREN_OPCD 0x06 /* Default Write Enable */ -#define HISI_SFLASH_NO_SPECIFIC_OPCD 0x00 -#define HISI_SFLASH_UNKOWN_OPCD 0xFF - -/********************************/ -/* ST M25Pxxx Device Specific */ -/********************************/ -/* Manufacturer IDs and Device IDs for SFLASHs supported by the driver */ -#define HISI_M25PXXX_ST_MANF_ID 0x20 -#define HISI_M25P80_DEVICE_ID 0x2014 -#define HISI_M25P80_MAX_SPI_FREQ 20000000 /* 20MHz */ -#define HISI_M25P80_MAX_FAST_SPI_FREQ 50000000 /* 50MHz */ -#define HISI_M25P80_FAST_READ_DUMMY_BYTES 1 -#define HISI_M25P32_DEVICE_ID 0x2016 -#define HISI_M25P32_MAX_SPI_FREQ 20000000 /* 20MHz */ -#define HISI_M25P32_MAX_FAST_SPI_FREQ 50000000 /* 50MHz */ -#define HISI_M25P32_FAST_READ_DUMMY_BYTES 1 -#define HISI_M25P64_DEVICE_ID 0x2017 -#define HISI_M25P64_MAX_SPI_FREQ 20000000 /* 20MHz */ -#define HISI_M25P64_MAX_FAST_SPI_FREQ 50000000 /* 50MHz */ -#define HISI_M25P64_FAST_READ_DUMMY_BYTES 1 -#define HISI_M25P128_DEVICE_ID 0x2018 -#define HISI_M25P128_MAX_SPI_FREQ 20000000 /* 20MHz */ -#define HISI_M25P128_MAX_FAST_SPI_FREQ 50000000 /* 50MHz */ -#define HISI_M25P128_FAST_READ_DUMMY_BYTES 1 - -/* Sector Sizes and population per device model */ -#define HISI_M25P80_SECTOR_SIZE 0x10000 /* 64K */ -#define HISI_M25P32_SECTOR_SIZE 0x10000 /* 64K */ -#define HISI_M25P64_SECTOR_SIZE 0x10000 /* 64K */ -#define HISI_M25P128_SECTOR_SIZE 0x40000 /* 256K */ -#define HISI_M25P80_SECTOR_NUMBER 16 -#define HISI_M25P32_SECTOR_NUMBER 64 -#define HISI_M25P64_SECTOR_NUMBER 128 -#define HISI_M25P128_SECTOR_NUMBER 64 -#define HISI_M25P_PAGE_SIZE 0x100 /* 256 byte */ - -#define HISI_M25P_WREN_CMND_OPCD 0x06 /* Write Enable */ -#define HISI_M25P_WRDI_CMND_OPCD 0x04 /* Write Disable */ -#define HISI_M25P_RDID_CMND_OPCD 0x9F /* Read ID */ -/* Read Status Register */ -#define HISI_M25P_RDSR_CMND_OPCD 0x05 -/* Write Status Register */ -#define HISI_M25P_WRSR_CMND_OPCD 0x01 -#define HISI_M25P_READ_CMND_OPCD 0x03 /* Sequential Read */ -#define HISI_M25P_FAST_RD_CMND_OPCD 0x0B /* Fast Read */ -#define HISI_M25P_PP_CMND_OPCD 0x02 /* Page Program */ -#define HISI_M25P_SSE_CMND_OPCD 0x20 /* SubSectorErase */ -#define HISI_M25P_SE_CMND_OPCD 0xD8 /* Sector Erase */ -#define HISI_M25P_BE_CMND_OPCD 0xC7 /* Bulk Erase */ -/* Read Electronic Signature */ -#define HISI_M25P_RES_CMND_OPCD 0xAB - -/* Status Register Write Protect Bit Masks - 3bits */ -#define HISI_M25P_STATUS_REG_WP_MASK (0x07 << HISI_SFLASH_STATUS_REG_WP_OFFSET) -#define HISI_M25P_STATUS_BP_NONE (0x00 << HISI_SFLASH_STATUS_REG_WP_OFFSET) -#define HISI_M25P_STATUS_BP_1_OF_64 (0x01 << HISI_SFLASH_STATUS_REG_WP_OFFSET) -#define HISI_M25P_STATUS_BP_1_OF_32 (0x02 << HISI_SFLASH_STATUS_REG_WP_OFFSET) -#define HISI_M25P_STATUS_BP_1_OF_16 (0x03 << HISI_SFLASH_STATUS_REG_WP_OFFSET) -#define HISI_M25P_STATUS_BP_1_OF_8 (0x04 << HISI_SFLASH_STATUS_REG_WP_OFFSET) -#define HISI_M25P_STATUS_BP_1_OF_4 (0x05 << HISI_SFLASH_STATUS_REG_WP_OFFSET) -#define HISI_M25P_STATUS_BP_1_OF_2 (0x06 << HISI_SFLASH_STATUS_REG_WP_OFFSET) -#define HISI_M25P_STATUS_BP_ALL (0x07 << HISI_SFLASH_STATUS_REG_WP_OFFSET) - -/************************************/ -/* MXIC MX25L6405 Device Specific */ -/************************************/ -/* Manufacturer IDs and Device IDs for SFLASHs supported by the driver */ -#define HISI_MXIC_MANF_ID 0xC2 -#define HISI_MX25L6405_DEVICE_ID 0x2017 -#define HISI_MX25L6405_MAX_SPI_FREQ 20000000 /* 20MHz */ -#define HISI_MX25L6405_MAX_FAST_SPI_FREQ 50000000 /* 50MHz */ -#define HISI_MX25L6405_FAST_READ_DUMMY_BYTES 1 -#define HISI_MXIC_DP_EXIT_DELAY 30 /* 30 ms */ - -/* Sector Sizes and population per device model */ -#define HISI_MX25L6405_SECTOR_SIZE 0x10000 /* 64K */ -#define HISI_MX25L6405_SECTOR_NUMBER 128 -#define HISI_MXIC_PAGE_SIZE 0x100 /* 256 byte */ - -#define HISI_MX25L_WREN_CMND_OPCD 0x06 /* Write Enable */ -#define HISI_MX25L_WRDI_CMND_OPCD 0x04 /* Write Disable */ -#define HISI_MX25L_RDID_CMND_OPCD 0x9F /* Read ID */ -/* Read Status Register */ -#define HISI_MX25L_RDSR_CMND_OPCD 0x05 -/* Write Status Register */ -#define HISI_MX25L_WRSR_CMND_OPCD 0x01 -#define HISI_MX25L_READ_CMND_OPCD 0x03 /* Sequential Read */ -#define HISI_MX25L_FAST_RD_CMND_OPCD 0x0B /* Fast Read */ -#define HISI_MX25L_PP_CMND_OPCD 0x02 /* Page Program */ -#define HISI_MX25L_SSE_CMND_OPCD 0x20 /* SubSector Erase */ -#define HISI_MX25L_SE_CMND_OPCD 0xD8 /* Sector Erase */ -#define HISI_MX25L_BE_CMND_OPCD 0xC7 /* Bulk Erase */ -#define HISI_MX25L_DP_CMND_OPCD 0xB9 /* Deep Power Down */ -/* Read Electronic Signature */ -#define HISI_MX25L_RES_CMND_OPCD 0xAB - -/* Status Register Write Protect Bit Masks - 4bits */ -#define HISI_MX25L_STATUS_REG_WP_MASK (0x0F << HISI_SFLASH_STATUS_REG_WP_OFFSET) -#define HISI_MX25L_STATUS_BP_NONE (0x00 << HISI_SFLASH_STATUS_REG_WP_OFFSET) -#define HISI_MX25L_STATUS_BP_1_OF_128 (0x01 << HISI_SFLASH_STATUS_REG_WP_OFFSET) -#define HISI_MX25L_STATUS_BP_1_OF_64 (0x02 << HISI_SFLASH_STATUS_REG_WP_OFFSET) -#define HISI_MX25L_STATUS_BP_1_OF_32 (0x03 << HISI_SFLASH_STATUS_REG_WP_OFFSET) -#define HISI_MX25L_STATUS_BP_1_OF_16 (0x04 << HISI_SFLASH_STATUS_REG_WP_OFFSET) -#define HISI_MX25L_STATUS_BP_1_OF_8 (0x05 << HISI_SFLASH_STATUS_REG_WP_OFFSET) -#define HISI_MX25L_STATUS_BP_1_OF_4 (0x06 << HISI_SFLASH_STATUS_REG_WP_OFFSET) -#define HISI_MX25L_STATUS_BP_1_OF_2 (0x07 << HISI_SFLASH_STATUS_REG_WP_OFFSET) -#define HISI_MX25L_STATUS_BP_ALL (0x0F << HISI_SFLASH_STATUS_REG_WP_OFFSET) - -/************************************/ -/* MXIC MX25LU12835F Device Specific */ -/************************************/ -/* Manufacturer IDs and Device IDs for SFLASHs supported by the driver */ -#define HISI_MX25U12835F_MANF_ID 0xC2 -#define HISI_MX25U12835F_DEVICE_ID 0x2538 -#define HISI_MX25U12835F_MAX_SPI_FREQ 20000000 /* 20MHz */ -#define HISI_MX25U12835F_MAX_FAST_SPI_FREQ 50000000 /* 50MHz */ -#define HISI_MX25U12835F_FAST_READ_DUMMY_BYTES 1 -#define HISI_MX25U12835F_DP_EXIT_DELAY 30 /* 30 ms */ - -/* Sector Sizes and population per device model */ -#define HISI_MX25U12835F_SECTOR_SIZE 0x10000 /* 64K */ -#define HISI_MX25U12835F_SECTOR_NUMBER 256 -#define HISI_MX25U12835F_PAGE_SIZE 0x1000 /* 4KB */ - -#define HISI_MX25U12835F_WREN_CMND_OPCD 0x06 /* Write Enable */ -#define HISI_MX25U12835F_WRDI_CMND_OPCD 0x04 /* Write Disable */ -#define HISI_MX25U12835F_RDID_CMND_OPCD 0x9F /* Read ID */ -/* Read Status Register */ -#define HISI_MX25U12835F_RDSR_CMND_OPCD 0x05 -/* Write Status Register */ -#define HISI_MX25U12835F_WRSR_CMND_OPCD 0x01 -#define HISI_MX25U12835F_READ_CMND_OPCD 0x03 /* Sequential Read */ -#define HISI_MX25U12835F_FAST_RD_CMND_OPCD 0x0B /* Fast Read */ -#define HISI_MX25U12835F_PP_CMND_OPCD 0x02 /* Page Program */ -#define HISI_MX25U12835F_SSE_CMND_OPCD 0x20 /* SubSector Erase */ -#define HISI_MX25U12835F_SE_CMND_OPCD 0xD8 /* Sector Erase */ -#define HISI_MX25U12835F_BE_CMND_OPCD 0xC7 /* Bulk Erase */ -#define HISI_MX25U12835F_DP_CMND_OPCD 0xB9 /* Deep Power Down */ -/* Read Electronic Signature */ -#define HISI_MX25U12835F_RES_CMND_OPCD 0xAB - -/* Status Register Write Protect Bit Masks - 4bits */ -#define HISI_MX25U12835F_STATUS_REG_WP_MASK (0x0F << HISI_SFLASH_STATUS_REG_WP_OFFSET) -#define HISI_MX25U12835F_STATUS_BP_NONE (0x00 << HISI_SFLASH_STATUS_REG_WP_OFFSET) -#define HISI_MX25U12835F_STATUS_BP_1_OF_128 (0x01 << HISI_SFLASH_STATUS_REG_WP_OFFSET) -#define HISI_MX25U12835F_STATUS_BP_1_OF_64 (0x02 << HISI_SFLASH_STATUS_REG_WP_OFFSET) -#define HISI_MX25U12835F_STATUS_BP_1_OF_32 (0x03 << HISI_SFLASH_STATUS_REG_WP_OFFSET) -#define HISI_MX25U12835F_STATUS_BP_1_OF_16 (0x04 << HISI_SFLASH_STATUS_REG_WP_OFFSET) -#define HISI_MX25U12835F_STATUS_BP_1_OF_8 (0x05 << HISI_SFLASH_STATUS_REG_WP_OFFSET) -#define HISI_MX25U12835F_STATUS_BP_1_OF_4 (0x06 << HISI_SFLASH_STATUS_REG_WP_OFFSET) -#define HISI_MX25U12835F_STATUS_BP_1_OF_2 (0x07 << HISI_SFLASH_STATUS_REG_WP_OFFSET) -#define HISI_MX25U12835F_STATUS_BP_ALL (0x0F << HISI_SFLASH_STATUS_REG_WP_OFFSET) - -/************************************/ -/* MXIC MX25L1606E Device Specific */ -/************************************/ -/* Manufacturer IDs and Device IDs for SFLASHs supported by the driver */ -#define HISI_MX25L1606E_DEVICE_ID 0x2015 -#define HISI_MX25L1606E_MAX_SPI_FREQ 33000000 /* 33MHz */ -#define HISI_MX25L1606E_MAX_FAST_SPI_FREQ 86000000 /* 86MHz */ -#define HISI_MX25L1606E_FAST_READ_DUMMY_BYTES 1 - -#define HISI_MX25L1606E_PAGE_SIZE 0x1000 /* 4K */ -#define HISI_MX25L1606E_SECTOR_SIZE 0x10000 /* 64K */ -#define HISI_MX25L1606E_SECTOR_NUMBER 32 - -/************************************/ -/* SPANSION S25Fx128 Device Specific */ -/************************************/ -/* Manufacturer IDs and Device IDs for SFLASHs supported by the driver */ -#define HISI_SPANSION_MANF_ID 0x01 -#define HISI_S25FL128_DEVICE_ID 0x2018 -#define HISI_S25FL128_MAX_SPI_FREQ 33000000 /* 33MHz */ -#define HISI_S25FL128_MAX_FAST_SPI_FREQ 104000000 /* 104MHz */ -#define HISI_S25FL128_FAST_READ_DUMMY_BYTES 1 - -/* Sector Sizes and population per device model */ -#define HISI_S25FL128_SECTOR_SIZE 0x10000 /* 64K */ -#define HISI_S25FL128_SECTOR_NUMBER 256 -#define HISI_S25FL_PAGE_SIZE 0x100 /* 256 byte */ - -#define HISI_S25FL_WREN_CMND_OPCD 0x06 /* Write Enable */ -#define HISI_S25FL_WRDI_CMND_OPCD 0x04 /* Write Disable */ -#define HISI_S25FL_RDID_CMND_OPCD 0x9F /* Read ID */ -/* Read Status Register */ -#define HISI_S25FL_RDSR_CMND_OPCD 0x05 -/* Write Status Register */ -#define HISI_S25FL_WRSR_CMND_OPCD 0x01 -#define HISI_S25FL_READ_CMND_OPCD 0x03 /* Sequential Read */ -#define HISI_S25FL_FAST_RD_CMND_OPCD 0x0B /* Fast Read */ -#define HISI_S25FL_PP_CMND_OPCD 0x02 /* Page Program */ -#define HISI_S25FL_SSE_CMND_OPCD 0x20 /* SubSector Erase */ -#define HISI_S25FL_SE_CMND_OPCD 0xD8 /* Sector Erase */ -#define HISI_S25FL_BE_CMND_OPCD 0xC7 /* Bulk Erase */ -#define HISI_S25FL_DP_CMND_OPCD 0xB9 /* Deep Power Down */ -/* Read Electronic Signature */ -#define HISI_S25FL_RES_CMND_OPCD 0xAB - -/* Status Register Write Protect Bit Masks - 4bits */ -#define HISI_S25FL_STATUS_REG_WP_MASK \ - (0x0F << HISI_SFLASH_STATUS_REG_WP_OFFSET) -#define HISI_S25FL_STATUS_BP_NONE \ - (0x00 << HISI_SFLASH_STATUS_REG_WP_OFFSET) -#define HISI_S25FL_STATUS_BP_1_OF_128 \ - (0x01 << HISI_SFLASH_STATUS_REG_WP_OFFSET) -#define HISI_S25FL_STATUS_BP_1_OF_64 \ - (0x02 << HISI_SFLASH_STATUS_REG_WP_OFFSET) -#define HISI_S25FL_STATUS_BP_1_OF_32 \ - (0x03 << HISI_SFLASH_STATUS_REG_WP_OFFSET) -#define HISI_S25FL_STATUS_BP_1_OF_16 \ - (0x04 << HISI_SFLASH_STATUS_REG_WP_OFFSET) -#define HISI_S25FL_STATUS_BP_1_OF_8 \ - (0x05 << HISI_SFLASH_STATUS_REG_WP_OFFSET) -#define HISI_S25FL_STATUS_BP_1_OF_4 \ - (0x06 << HISI_SFLASH_STATUS_REG_WP_OFFSET) -#define HISI_S25FL_STATUS_BP_1_OF_2 \ - (0x07 << HISI_SFLASH_STATUS_REG_WP_OFFSET) -#define HISI_S25FL_STATUS_BP_ALL \ - (0x0F << HISI_SFLASH_STATUS_REG_WP_OFFSET) - -/********************************/ -/* ATMEL ATxx Device Specific */ -/********************************/ -/* Manufacturer IDs and Device IDs for SFLASHs supported by the driver */ -#define HISI_AT25DFXXX_AT_MANF_ID 0x1F -#define HISI_AT25DF641_DEVICE_ID 0x4800 -#define HISI_AT25DF641_MAX_SPI_FREQ 20000000 /* 20MHz */ -#define HISI_AT25DF641_MAX_FAST_SPI_FREQ 50000000 /* 50MHz */ -#define HISI_AT25DF641_FAST_READ_DUMMY_BYTES 1 - -/* Sector Sizes and population per device model */ -#define HISI_AT25DF641_SECTOR_SIZE 0x10000 /* 64K */ -#define HISI_AT25DF641_SECTOR_NUMBER 128 -#define HISI_AT25DF_PAGE_SIZE 0x100 /* 256 byte */ - -#define HISI_AT25DF_WREN_CMND_OPCD 0x06 /* Write Enable */ -#define HISI_AT25DF_WRDI_CMND_OPCD 0x04 /* Write Disable */ -#define HISI_AT25DF_RDID_CMND_OPCD 0x9F /* Read ID */ -#define HISI_AT25DF_RDSR_CMND_OPCD 0x05 /* Read Status Register */ -#define HISI_AT25DF_WRSR_CMND_OPCD 0x01 /* Write Status Register */ -#define HISI_AT25DF_READ_CMND_OPCD 0x03 /* Sequential Read */ -#define HISI_AT25DF_FAST_RD_CMND_OPCD 0x0B /* Fast Read */ -#define HISI_AT25DF_PP_CMND_OPCD 0x02 /* Page Program */ -#define HISI_AT25DF_SSE_CMND_OPCD 0x20 /* SubSector Erase */ -#define HISI_AT25DF_SE_CMND_OPCD 0xD8 /* Sector Erase */ -#define HISI_AT25DF_BE_CMND_OPCD 0xC7 /* Bulk Erase */ -#define HISI_AT25DF_RES_CMND_OPCD 0xAB /* Read Electronic Signature */ - -/* Status Register Write Protect Bit Masks - 4bits */ -#define HISI_AT25DF_STATUS_REG_WP_MASK \ - (0x0F << HISI_SFLASH_STATUS_REG_WP_OFFSET) -#define HISI_AT25DF_STATUS_BP_NONE \ - (0x00 << HISI_SFLASH_STATUS_REG_WP_OFFSET) - -#define HISI_AT25DF_STATUS_BP_WP_NONE (0x04 << HISI_SFLASH_STATUS_REG_WP_OFFSET) -#define HISI_AT25DF_STATUS_BP_SOME (0x05 << HISI_SFLASH_STATUS_REG_WP_OFFSET) -#define HISI_AT25DF_STATUS_BP_ALL (0x07 << HISI_SFLASH_STATUS_REG_WP_OFFSET) - -/********************************/ -/* NUMONYX N25Q Device Specific */ -/********************************/ -#define HISI_N25Q_WREN_CMND_OPCD 0x06 /* Write Enable */ -#define HISI_N25Q_WRDI_CMND_OPCD 0x04 /* Write Disable */ -#define HISI_N25Q_RDID_CMND_OPCD 0x9F /* Read ID */ -/* Read Status Register */ -#define HISI_N25Q_RDSR_CMND_OPCD 0x05 -/* Write Status Register */ -#define HISI_N25Q_WRSR_CMND_OPCD 0x01 -#define HISI_N25Q_READ_CMND_OPCD 0x03 /* Sequential Read */ -#define HISI_N25Q_FAST_RD_CMND_OPCD 0x0B /* Fast Read */ -#define HISI_N25Q_PP_CMND_OPCD 0x02 /* Page Program */ -#define HISI_N25Q_SSE_CMND_OPCD 0x20 /* SubSectorErase */ -#define HISI_N25Q_SE_CMND_OPCD 0xD8 /* Sector Erase */ -#define HISI_N25Q_BE_CMND_OPCD 0xC7 /* Bulk Erase */ -/* Read Volatile Enhanced Configuration Register */ -#define HISI_N25Q_RDVECR_CMND_OPCD 0x65 -/* Write Volatile Enhanced Configuration Register */ -#define HISI_N25Q_WRVECR_CMND_OPCD 0x61 -/* Enter 4-byte address mode */ -#define HISI_N25Q_EN4BADDR_CMND_OPCD 0xB7 -/* Exit 4-byte address mode */ -#define HISI_N25Q_EX4BADDR_CMND_OPCD 0xE9 -/* STATUS REGISTER BUSY BIT */ -#define HISI_N25Q_BUSY_FLAG_BIT 0xC7 - -#define HISI_N25Q256_MANF_ID 0x20 -#define HISI_N25Q256_DEVICE_ID 0xBA19 -#define HISI_N25Q256_MAX_SPI_FREQ 108000000 /* 108MHz */ -#define HISI_N25Q256_MAX_FAST_SPI_FREQ 432000000 /* 432MHz */ -#define HISI_N25Q256_FAST_READ_DUMMY_BYTES 8 - -#define HISI_N25Q256_SECTOR_SIZE 0x10000 /* 64K */ -#define HISI_N25Q256_SECTOR_NUMBER 512 -#define HISI_N25Q256_PAGE_SIZE 0x1000 /* 4K */ - -/* support 3byte and 4byte addr */ -#define HISI_N25Q256_3B_4B_SUPPORT 0x3 -/* support ESPI, FULL DIO, FULL QIO mode */ -#define HISI_N25Q256_IF_TYPE_SUPPORT 0x89 - -#define HISI_N25Q128_MANF_ID 0x20 -#define HISI_N25Q128_DEVICE_ID 0xBA18 -#define HISI_N25Q128_MAX_SPI_FREQ 108000000 /* 108MHz */ -#define HISI_N25Q128_MAX_FAST_SPI_FREQ 432000000 /* 432MHz */ -#define HISI_N25Q128_FAST_READ_DUMMY_BYTES 8 - -#define HISI_N25Q128_SECTOR_SIZE 0x10000 /* 64K */ -#define HISI_N25Q128_SECTOR_NUMBER 256 -#define HISI_N25Q128_PAGE_SIZE 0x1000 /* 4K */ - -/* NUMONYX N25Q128B SPI flash */ -#define HISI_N25Q128B_MANF_ID 0x20 -#define HISI_N25Q128B_DEVICE_ID 0xBB18 - -/* support 3byte and 4byte addr */ -#define HISI_N25Q128_3B_4B_SUPPORT 0x3 -/* support ESPI, FULL DIO, FULL QIO mode */ -#define HISI_N25Q128_IF_TYPE_SUPPORT 0x89 - -#endif