From: Zhou Guanghui zhouguanghui1@huawei.com
ascend inclusion category: feature bugzilla: NA CVE: NA
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Add Message Base SPI optional property for hisilicon
Signed-off-by: Zhou Guanghui zhouguanghui1@huawei.com Reviewed-by: Ding Tianhong dingtianhong@huawei.com Signed-off-by: Yang Yingliang yangyingliang@huawei.com --- Documentation/devicetree/bindings/iommu/arm,smmu-v3.txt | 8 ++++++++ 1 file changed, 8 insertions(+)
diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu-v3.txt b/Documentation/devicetree/bindings/iommu/arm,smmu-v3.txt index c9abbf3e4f682..322f958939fb4 100644 --- a/Documentation/devicetree/bindings/iommu/arm,smmu-v3.txt +++ b/Documentation/devicetree/bindings/iommu/arm,smmu-v3.txt @@ -61,6 +61,14 @@ the PCIe specification. Set for Cavium ThunderX2 silicon that doesn't support SMMU page1 register space.
+- hisilicon,message-based-spi + : Message based SPI is used for Ascend310 silicon. The addr + of GICD_SETSPIR needs to be configured in the CFG_REG of + SMMU. + +- iommu-spi-base + : The addr of GICD_SETSPI + ** Example
smmu@2b400000 {