From: Victor Ding victording@google.com
mainline inclusion from mainline-5.16-rc7 commit 298ed2b31f55280624417f80a09de0e28db8f786 category: feature feature: milan cpu bugzilla: https://gitee.com/openeuler/kernel/issues/I4NX57 CVE: NA
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MSRs in the rest of this file are sorted by their addresses; fixing the two outliers.
No functional changes.
Signed-off-by: Victor Ding victording@google.com Acked-by: Kim Phillips kim.phillips@amd.com Signed-off-by: Rafael J. Wysocki rafael.j.wysocki@intel.com Signed-off-by: qinyu qinyu16@huawei.com Reviewed-by: Chao Liu liuchao173@huawei.com Reviewed-by: Xiongfeng Wang wangxiongfeng2@huawei.com Signed-off-by: Zheng Zengkai zhengzengkai@huawei.com --- arch/x86/include/asm/msr-index.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h index 972a34d93505..21917e134ad4 100644 --- a/arch/x86/include/asm/msr-index.h +++ b/arch/x86/include/asm/msr-index.h @@ -326,8 +326,8 @@ #define MSR_PP1_ENERGY_STATUS 0x00000641 #define MSR_PP1_POLICY 0x00000642
-#define MSR_AMD_PKG_ENERGY_STATUS 0xc001029b #define MSR_AMD_RAPL_POWER_UNIT 0xc0010299 +#define MSR_AMD_PKG_ENERGY_STATUS 0xc001029b
/* Config TDP MSRs */ #define MSR_CONFIG_TDP_NOMINAL 0x00000648