Breno Leitao (1): perf/x86/amd/core: Always clear status for idx
Sandipan Das (1): perf/x86/amd/core: Fix overflow reset on hotplug
arch/x86/events/amd/core.c | 17 ++++++++++------- 1 file changed, 10 insertions(+), 7 deletions(-)
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From: Breno Leitao leitao@debian.org
mainline inclusion from mainline-v6.3-rc4 commit 263f5ecaf7080513efc248ec739b6d9e00f4129f category: bugfix bugzilla: https://gitee.com/openeuler/kernel/issues/IAMTVA Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?i...
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The variable 'status' (which contains the unhandled overflow bits) is not being properly masked in some cases, displaying the following warning:
WARNING: CPU: 156 PID: 475601 at arch/x86/events/amd/core.c:972 amd_pmu_v2_handle_irq+0x216/0x270
This seems to be happening because the loop is being continued before the status bit being unset, in case x86_perf_event_set_period() returns 0. This is also causing an inconsistency because the "handled" counter is incremented, but the status bit is not cleaned.
Move the bit cleaning together above, together when the "handled" counter is incremented.
Fixes: 7685665c390d ("perf/x86/amd/core: Add PerfMonV2 overflow handling") Signed-off-by: Breno Leitao leitao@debian.org Signed-off-by: Peter Zijlstra (Intel) peterz@infradead.org Reviewed-by: Sandipan Das sandipan.das@amd.com Link: https://lore.kernel.org/r/20230321113338.1669660-1-leitao@debian.org Signed-off-by: Luo Gengkun luogengkun2@huawei.com --- arch/x86/events/amd/core.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/arch/x86/events/amd/core.c b/arch/x86/events/amd/core.c index 3127519281f5..d0ba30a6499d 100644 --- a/arch/x86/events/amd/core.c +++ b/arch/x86/events/amd/core.c @@ -956,6 +956,7 @@ static int amd_pmu_v2_handle_irq(struct pt_regs *regs)
/* Event overflow */ handled++; + status &= ~mask; perf_sample_data_init(&data, 0, hwc->last_period);
if (!x86_perf_event_set_period(event)) @@ -963,8 +964,6 @@ static int amd_pmu_v2_handle_irq(struct pt_regs *regs)
if (perf_event_overflow(event, &data, regs)) x86_pmu_stop(event, 0); - - status &= ~mask; }
/*
From: Sandipan Das sandipan.das@amd.com
mainline inclusion from mainline-v6.6-rc4 commit 23d2626b841c2adccdeb477665313c02dff02dc3 category: bugfix bugzilla: https://gitee.com/openeuler/kernel/issues/IAMTVO
Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?i...
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Kernels older than v5.19 do not support PerfMonV2 and the PMI handler does not clear the overflow bits of the PerfCntrGlobalStatus register. Because of this, loading a recent kernel using kexec from an older kernel can result in inconsistent register states on Zen 4 systems.
The PMI handler of the new kernel gets confused and shows a warning when an overflow occurs because some of the overflow bits are set even if the corresponding counters are inactive. These are remnants from overflows that were handled by the older kernel.
During CPU hotplug, the PerfCntrGlobalCtl and PerfCntrGlobalStatus registers should always be cleared for PerfMonV2-capable processors. However, a condition used for NB event constaints applicable only to older processors currently prevents this from happening. Move the reset sequence to an appropriate place and also clear the LBR Freeze bit.
Fixes: 21d59e3e2c40 ("perf/x86/amd/core: Detect PerfMonV2 support") Signed-off-by: Sandipan Das sandipan.das@amd.com Signed-off-by: Ingo Molnar mingo@kernel.org Link: https://lore.kernel.org/r/882a87511af40792ba69bb0e9026f19a2e71e8a3.169469688...
Conflicts: arch/x86/events/amd/core.c [Fix contexts conflicts]
Signed-off-by: Luo Gengkun luogengkun2@huawei.com --- arch/x86/events/amd/core.c | 14 +++++++++----- 1 file changed, 9 insertions(+), 5 deletions(-)
diff --git a/arch/x86/events/amd/core.c b/arch/x86/events/amd/core.c index d0ba30a6499d..e1b00e5c0486 100644 --- a/arch/x86/events/amd/core.c +++ b/arch/x86/events/amd/core.c @@ -591,8 +591,12 @@ static void amd_pmu_cpu_reset(int cpu) /* Clear enable bits i.e. PerfCntrGlobalCtl.PerfCntrEn */ wrmsrl(MSR_AMD64_PERF_CNTR_GLOBAL_CTL, 0);
- /* Clear overflow bits i.e. PerfCntrGLobalStatus.PerfCntrOvfl */ - wrmsrl(MSR_AMD64_PERF_CNTR_GLOBAL_STATUS_CLR, amd_pmu_global_cntr_mask); + /* + * Clear freeze and overflow bits i.e. PerfCntrGLobalStatus.LbrFreeze + * and PerfCntrGLobalStatus.PerfCntrOvfl + */ + wrmsrl(MSR_AMD64_PERF_CNTR_GLOBAL_STATUS_CLR, + GLOBAL_STATUS_LBRS_FROZEN | amd_pmu_global_cntr_mask); }
static int amd_pmu_cpu_prepare(int cpu) @@ -619,6 +623,7 @@ static void amd_pmu_cpu_starting(int cpu) int i, nb_id;
cpuc->perf_ctr_virt_mask = AMD64_EVENTSEL_HOSTONLY; + amd_pmu_cpu_reset(cpu);
if (!x86_pmu.amd_nb_constraints) return; @@ -642,13 +647,14 @@ static void amd_pmu_cpu_starting(int cpu) cpuc->amd_nb->refcnt++;
amd_brs_reset(); - amd_pmu_cpu_reset(cpu); }
static void amd_pmu_cpu_dead(int cpu) { struct cpu_hw_events *cpuhw;
+ amd_pmu_cpu_reset(cpu); + if (!x86_pmu.amd_nb_constraints) return;
@@ -662,8 +668,6 @@ static void amd_pmu_cpu_dead(int cpu)
cpuhw->amd_nb = NULL; } - - amd_pmu_cpu_reset(cpu); }
static inline void amd_pmu_set_global_ctl(u64 ctl)
-
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