[Acc] Re: UADK + MD5 软加速集成设计

On 2022/5/24 下午5:28, Guodong Xu wrote:

Hi, All

Attached please find the draft design. Let me know what you think.

1. Do we have to realize both the left algo layer, and right driver layer?

2. The interface wd_do_digest_async & wd_do_digest_sync are already realized. So we reuse the same interface. How to distinguish between hardware accelerator and mb

3. What's the goal. Do we need support switch between hardware accelerator and mb?

Thanks

Thanks. BR, Guodong

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