On Tue, Jan 19, 2021 at 10:04:23AM +0000, Shiju Jose wrote:
This EDAC code for the cache errors is architecture independent for the firmware-first error reporting and could be used for other architectures,
I'm not so sure about that because you're lumping all the cache hierarchies together and there might be L3 slices on some x86 incarnations, for example, which do not belong to the core you're reporting the error for... It would need to be tested though.
Also, if this is a firmware-first mode, then I would expect the firmware to also report which cache triggered the error and thus not need any OS glue at all.
Therefore ARM only and I'd need an ACK from ARM folks whether they want it this way.
Thx.